Integrated Circuits (ICs) are widely used in all applications and industries like smart cards, cell phones, set-top boxes, automobiles, avionics, space exploration and bio-instrumentation, to name a few. Traditional IC design flows and architectural synthesis techniques have been developed primarily for area, power and performance optimization. In recent years, as we move into the nanometer semiconductor process era, the ability to integrate large and complex applications on a single semiconductor die coupled with the all pervasive nature of the technology and its impact on our daily lives, have brought into prominence two important IC optimization constraints: Security and Correctness.
In this thesis, we have developed novel architectural synthesis techniques at cell-level, circuit-level and algorithmic-level, in a hierarchical standard-cell-based IC design framework, to design correct and secure ICs. Formulation as a hierarchical framework allows efficient partitioning of the design problem into several clearly-defined design steps at various levels of abstractions, with a clear understanding of each design step and ability to incorporate the requirements of subsequent design steps. Furthermore, unlike naive security-centric IC design flows where security and IC implementation constraints (area, power and performance) are typically considered as orthogonal and often conflicting optimization goals, in this thesis, we developed a novel paradigm that could be used to simultaneously optimize security as well as IC implementation constraints (area and power), at various hierarchical levels of IC design. Together, these architectural synthesis techniques fit well in today's highly productive modular IC design flows, and thus efficiently design correct and secure ICs.