Dramatic improvements in semiconductor integrated circuit technology presently make it possible to integrate millions of transistors, onto a single semiconductor IC. These improvements in integration densities have been driven by aggressive scaling of technology, which has led to both increasing density and computing power.
On the flip side, constant drive towards ever decreasing feature sizes has led to a signicant increase in manufacturing cost. One of the main causes of this increase in manufacturing cost is a signicant decrease in manufacturing yield due to manufacturing losses. These manufacturing losses are due to increasing process parameter variations that CMOS devices face at nanometer scale.
Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For Digital Signal Processing (DSP) hardware, variations in circuit parameters can signicantly aect the Quality of Service (QoS). Post-silicon calibration and repair have emerged as an eective solution to maintain QoS in DSP chips under large process-induced parameter variations. However, existing calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, fre-
quency or body bias and typically incur large delay or power overhead. In this thesis, a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts is presented. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least signicant bits. Hence, truncation of these bits, by setting them at constant values, can eectively reduce the delay of a unit, thereby avoiding delay failures. Efficient choice of truncation bits and values can minimize the impact of truncation on QoS. Appropriate design time modications including insertion of low-overhead truncation circuit and skewing the path delay distribution through gate sizing to maximize the delay improvement with truncation are presented.
The proposed technique is applied on two common DSP circuits, namely Discrete Cosine Transform (DCT) and Finite Impulse Response (FIR). Simulation results show signicant decrease in critical path delay with the truncation of least signicant input bits and a graceful degradation in the QoS. Also there is a large improvement
in manufacturing yield (41:6%) with up to 5X savings in power compared to existing approaches like voltage scaling and body biasing.