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Han, QiangOn Resilient System Testing and Performance Binning
PhD, University of Cincinnati, 2015, Engineering and Applied Science: Computer Science and Engineering
By allowing timing errors to occur and recovering them on-line, resilient systems are designed to eliminate the frequency or voltage margin to improve circuit performance or reduce power consumption. With the existence of error detection and correction circuits, resilient systems bring about new timing constraints for path delay testing. With the characteristics of allowing timing errors to occur and recovering them on-line, the metrics of resilient system performance are different from traditional circuits, which results in new challenges on resilient system performance binning. Due to these new characteristics of resilient systems, it is essential to develop new testing and binning methodologies for them. In this research, we focus on resilient system testing and performance binning, and attempt to push forward the pace of resilient system commercialization. We make the following contributions. First, we propose a new DFT (design-for-testability) technique, which is able to deal with all different types of timing faults existing in resilient systems, and we develop an efficient test method based on binary search for error collection circuits. Then, a performance binning method based on structural at-speed delay testing is developed for resilient systems to greatly save the binning cost, and an adaptive clock configuration technique is proposed for yield improvement. Last but not least, we propose a new statistical performance analysis tool for resilient systems, called SERA (statistical error rate analysis), which takes process variations into consideration for error rate analysis and produces performance distribution function. With the help of SERA, we develop a profit-oriented binning methodology for resilient systems.

Committee:

Wen-Ben Jone, Ph.D. (Committee Chair); Chien-In Henry Chen, Ph.D. (Committee Member); Harold Carter, Ph.D. (Committee Member); Carla Purdy, Ph.D. (Committee Member); Ranganadha Vemuri, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Resilient computing;Delay testing;Performance binning;Yield improvement;Error rate modeling;Statistical analysis

Kunaparaju, KeerthiVaROT: Methodology for Variation-Tolerant DSP Hardware Design using Post-Silicon Truncation of Operand Width
Master of Sciences, Case Western Reserve University, 2011, EECS - Computer Engineering

Dramatic improvements in semiconductor integrated circuit technology presently make it possible to integrate millions of transistors, onto a single semiconductor IC. These improvements in integration densities have been driven by aggressive scaling of technology, which has led to both increasing density and computing power.

On the flip side, constant drive towards ever decreasing feature sizes has led to a signicant increase in manufacturing cost. One of the main causes of this increase in manufacturing cost is a signicant decrease in manufacturing yield due to manufacturing losses. These manufacturing losses are due to increasing process parameter variations that CMOS devices face at nanometer scale.

Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For Digital Signal Processing (DSP) hardware, variations in circuit parameters can signicantly aect the Quality of Service (QoS). Post-silicon calibration and repair have emerged as an eective solution to maintain QoS in DSP chips under large process-induced parameter variations. However, existing calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, fre- quency or body bias and typically incur large delay or power overhead. In this thesis, a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts is presented. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least signicant bits. Hence, truncation of these bits, by setting them at constant values, can eectively reduce the delay of a unit, thereby avoiding delay failures. Efficient choice of truncation bits and values can minimize the impact of truncation on QoS. Appropriate design time modications including insertion of low-overhead truncation circuit and skewing the path delay distribution through gate sizing to maximize the delay improvement with truncation are presented.

The proposed technique is applied on two common DSP circuits, namely Discrete Cosine Transform (DCT) and Finite Impulse Response (FIR). Simulation results show signicant decrease in critical path delay with the truncation of least signicant input bits and a graceful degradation in the QoS. Also there is a large improvement in manufacturing yield (41:6%) with up to 5X savings in power compared to existing approaches like voltage scaling and body biasing.

Committee:

Swarup Bhunia (Committee Chair); Christous Papachristou (Committee Member); Francis "Frank" Merat (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Post-Silicon Repair; DSP; Quality of Service; Operand Truncation; Yield Improvement