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Han, QiangOn Resilient System Testing and Performance Binning
PhD, University of Cincinnati, 2015, Engineering and Applied Science: Computer Science and Engineering
By allowing timing errors to occur and recovering them on-line, resilient systems are designed to eliminate the frequency or voltage margin to improve circuit performance or reduce power consumption. With the existence of error detection and correction circuits, resilient systems bring about new timing constraints for path delay testing. With the characteristics of allowing timing errors to occur and recovering them on-line, the metrics of resilient system performance are different from traditional circuits, which results in new challenges on resilient system performance binning. Due to these new characteristics of resilient systems, it is essential to develop new testing and binning methodologies for them. In this research, we focus on resilient system testing and performance binning, and attempt to push forward the pace of resilient system commercialization. We make the following contributions. First, we propose a new DFT (design-for-testability) technique, which is able to deal with all different types of timing faults existing in resilient systems, and we develop an efficient test method based on binary search for error collection circuits. Then, a performance binning method based on structural at-speed delay testing is developed for resilient systems to greatly save the binning cost, and an adaptive clock configuration technique is proposed for yield improvement. Last but not least, we propose a new statistical performance analysis tool for resilient systems, called SERA (statistical error rate analysis), which takes process variations into consideration for error rate analysis and produces performance distribution function. With the help of SERA, we develop a profit-oriented binning methodology for resilient systems.

Committee:

Wen-Ben Jone, Ph.D. (Committee Chair); Chien-In Henry Chen, Ph.D. (Committee Member); Harold Carter, Ph.D. (Committee Member); Carla Purdy, Ph.D. (Committee Member); Ranganadha Vemuri, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Resilient computing;Delay testing;Performance binning;Yield improvement;Error rate modeling;Statistical analysis

Nilamboor, Sanjay NA Study on Performance Binning in Error Resilient Circuits
MS, University of Cincinnati, 2015, Engineering and Applied Science: Electrical Engineering
In recent times, feature sizes of integrated circuits are shrinking and performance is on an upward trend. This has led to several interesting research ideas focussed on improving performance and error resilience, such as EDS [1]. An error resilient design has the capability to detect and recover from errors during normal operation, and can improve performance by eliminating the need for frequency guard bands and thus, paving way for higher speeds of operation. Our work tries to address the new challenges encountered while characterizing the performance of such chips. This work addresses two major aspects of performance binning in error resilient designs. Firstly, we outline a framework built using industry standard tools for performing timing analyses and performance binning of error resilient chips. Based on the throughput of a circuit employing error resilience at different frequencies, the performance binning process can be fine-tuned to improve efficiency and reduce wastage. Second, we explore the relationship between error count using path delay tests and error rate using functional benchmark programs in error resilient designs. We have performed experiments on a commercial chip using path delay tests and functional benchmark patterns. Our results demonstrate the feasibility of using delay testing to replace the time consuming functional binning process which usually is very expensive, especially for error resilient computing.

Committee:

Wen-Ben Jone, Ph.D. (Committee Chair); Carla Purdy, Ph.D. (Committee Member); Ranganadha Vemuri, Ph.D. (Committee Member)

Subjects:

Electrical Engineering

Keywords:

performance binning;atpg;delay test patterns