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Wang, MingyangImproving Performance And Reliability Of Flash Memory Based Solid State Storage Systems
PhD, University of Cincinnati, 2016, Engineering and Applied Science: Computer Science and Engineering
Flash memory based Solid State Disk systems (SSDs) are becoming increasingly popular in enterprise applications where high performance and high reliability are paramount. While SSDs outperform traditional Hard Disk Drives (HDDs) in read and write operations, they pose some unique and serious challenges to I/O and file system designers. The performance of an SSD has been found to be sensitive to access patterns. Specifically read operations perform much faster than write ones, and sequential accesses deliver much higher performance than random accesses. The unique properties of SSDs, together with the asymmetric overheads of different operations, imply that many traditional solutions tailored for HDDs may not work well for SSDs. The close relation between performance overhead and access patterns motivates us to design a series of novel algorithms for I/O scheduler and buffer cache management. By exploiting refined access patterns such as sequential, page clustering, block clustering in a per-process per-file manner, a series of innovative algorithms on I/O scheduler and buffer cache can deliver higher performance of the file system and SSD devices. Other than the performance issues, SSDs also face some unique reliability challenges due to the natural properties of flash memory. Along with the well-known write-endurance, flash memory also suffers from read-disturb and write-disturb. Even repeatedly reading from an SSD may cause data corruption because the read voltage may stress neighboring memory cells. As the density of flash memory keeps increasing, the disturbing problems are becoming even more severe for memory cells to store data reliably. One of the structural merits of an SSD is its internal parallelism. Such parallelism of flash memory chips could be exploited to support data redundancy in a similar fashion to traditional HDD RAID. Recently an emerging non-volatile memory (NVM) such as PCM is receiving increasing research interest, as it outperforms flash memory by providing in-place update and better performance and reliability. Hybrid solutions, which combine both flash memory and NVM to balance performance and cost, are under special investigation to address the reliability and performance issues of flash memory based storage systems. To address the reliability concerns, we present a novel storage architecture called i-RAID (internal RAID) that introduces RAID-like parity-based redundancy while avoiding many of its problems. What make i-RAID so unique like no other are its deferred parity maintenance, selective RAID protection and dynamic RAID organization. It solves traditional RAID’s small update problem and avoids SSD RAID pitfalls. Unlike traditional disk drives, SSDs cannot perform in-place updates. We view this unique characteristic as an opportunity instead of a hurdle. The out-of-place update feature means that old data will not be over-written by the new data, which enables us to design some fundamentally new algorithms that defer the computing and updating of parity blocks until the garbage collection time, thereby significantly reducing the overhead and possibly increasing the life-time of SSDs. Our algorithms also dynamically and selectively construct parity stripes only on aged, error-prone blocks, and utilize the internal parallelism of SSDs to further improve performance.

Committee:

Yiming Hu, Ph.D. (Committee Chair); Kenneth Berman, Ph.D. (Committee Member); Karen Davis, Ph.D. (Committee Member); Wen-Ben Jone, Ph.D. (Committee Member); Carla Purdy, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Flash Memory;RAID;Solid State Disk;Non Volatile Memory;Write Endurance;Read Write Disturb

Chowdhury, MadhumitaNiOx Based Resistive Random Access Memories
Master of Science in Electrical Engineering, University of Toledo, 2012, Electrical Engineering
In present flash memory devices, data is stored by injecting hot electrons or charge through tunnel oxide. This will result into degradation of oxide and the problem would amplify with the scaling of the dielectric. According to International Technology Roadmap for Semiconductors (ITRS) the continuous scaling of the oxide thickness beyond 16 nm node technology may result into unwanted data loss and high leakage current. Hence, new ways of data storage are being explored, resistive random access memory (RRAM) being one of them. A RRAM device is a two-terminal metal insulator metal (MIM) structure having the potential to scale up to 8 nm generation technology. It is non-volatile and can store data in form of both low resistance state (LRS) and high resistance state (HRS). The other incentives are its low operating voltage, high endurance and integration in crossbar arrays. NiOx promises to be a strong candidate for future non-volatile memory devices and it still needs a better understanding of the physical mechanism behind the ability to switch between two resistive states. This thesis is focused to study the impact of different metal electrode on NiOx based RRAM devices with high percentage (20%) of O2.RRAM device performance with Al and Ru electrodes was studied. Switching characteristics indicated that Al based electrodes lead to the device failure due to formation Al2O3 on NiOx. On the other hand, devices with Ru electrodes demonstrated switching with SET/RESET voltages of less than ±2 V. Moreover, the conduction mechanism responsible for switching mechanism is also reported.

Committee:

Rashmi Jha, PhD (Committee Chair); Vijay Devabhaktuni, PhD (Committee Co-Chair); Mansoor Alam, PhD (Committee Member); Christopher Melkonian, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Nickel oxide; non-volatile memory; resistive switching; RRAM

Sundararajan, MayurAmorphous Semiconductors: From Photocatalyst to Computer Memory
Doctor of Philosophy (PhD), Ohio University, 2017, Physics and Astronomy (Arts and Sciences)
Amorphous semiconductors are useful in many applications like solar cells, thin film displays, sensors, electrophotography, etc. The dissertation contains four projects. In the first three projects, semiconductor glasses which are a subset of amorphous semiconductors were studied. The last project is about exploring the strengths and constraints of two analysis programs which calculate the particle size information from experimental Small Angle X-ray Scattering data. By definition, glasses have a random atomic arrangement with no order beyond the nearest neighbor, but strangely there exists an Intermediate Range Order (IRO). The origin of IRO is still not clearly understood, but various models have been proposed. The signature of IRO is the First Sharp Diffraction Peak(FSDP) observed in x-ray and neutron scattering data. The FSDP of TiO2 SiO2 glass photocatalyst with different Ti:Si ratio from SAXS data was measured to test the theoretical models. The experimental results along with its computer simulation results strongly supported one of two leading models. It was also found that the effect of doping IRO on TiO2 SiO2 is severe in mesoporous form than the bulk form. Glass semiconductors in mesoporous form are very useful photocatalysts due to their large specific surface area. Solar energy conversion of photocatalysts greatly depends on their bandgap, but very few photocatalysts have the optical bandgap covering the whole visible region of solar spectrum leading to poor efficiency. A physical method was developed to manipulate the bandgap of mesoporous photocatalysts, by using the anisotropic thermal expansion and stressed glass network properties of mesoporous glasses. The anisotropic thermal expansion was established by S/WAXS characterization of mesoporous silica (MCM-41). The residual stress in the glass network of mesoporous glasses was already known for an earlier work. The new method was initially applied on mesoporous TiPO4, and the results were encouraging but inconclusive. Then the method was successfully demonstrated on mesoporous TiO2SiO2 by showing a shift in its optical bandgap. One of the special class of amorphous semiconductors is chalcogenide glasses, which exhibit high ionic conductivity even at room temperature. When metal doped chalcogenide glasses are under an electric field, they become electronically conductive. These properties are exploited in the computer memory storage application of Conductive Bridging Random Access Memory (CBRAM). CBRAM is a non-volatile memory that is a strong contender to replace conventional volatile RAMs such as DRAM, SRAM, etc. This technology has already been commercialized, but the working mechanism is still not clearly understood especially the nature of the conductive bridge filament. In this project, the CBRAM memory cells are fabricated by thermal evaporation method with Agx(GeSe2) 1-x as the solid electrolyte layer, Ag as the active electrode and Au as the inert electrode. By careful use of cyclic voltammetry, the conductive filaments were grown on the surface and the bulk of the solid electrolyte. The comparison between the two filaments revealed major differences leading to contradiction with the existing working mechanism. After compiling all the results, a modified working mechanism is proposed. SAXS is a powerful tool to characterize nanostructure of glasses. The analysis of the SAXS data to get useful information are usually performed by different programs. In this project, Irena and GIFT programs were compared by performing the analysis of the SAXS data of glass and glass ceramics samples. Irena was shown to be not suitable for the analysis of SAXS data that has a significant contribution from interparticle interactions. GIFT was demonstrated to be better suited for such analysis. Additionally, the results obtained by programs for samples with low interparticle interactions were shown to be consistent.

Committee:

Gang Chen, PhD (Advisor)

Subjects:

Materials Science; Physics

Keywords:

CBRAM; Non-Volatile Memory; Photocatalysts; Bandgap Engineering; Silica; FSDP; Intermediate Range Order; Irena; SAXS; SEM; Chalcogenide Glasses; Sol-gel synthesis

Pan, XiangDesigning Future Low-Power and Secure Processors with Non-Volatile Memory
Doctor of Philosophy, The Ohio State University, 2017, Computer Science and Engineering
Non-volatile memories such as Spin-Transfer Torque Random Access Memory (STT-RAM), Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), etc. are emerging as promising alternatives to DRAM and SRAM. These new memory technologies have many exciting characteristics such as non-volatility, high density, and near-zero leakage power. These features make them very good candidates for future processor designs in the power-hungry big data era. STT-RAM, a new generation of Magnetoresistive RAM, in particular is an attractive class of non-volatile memory because it has infinite write endurance, good compatibility with CMOS technology, fast read speed, and low read energy. With its good read performance and high endurance, it is feasible to replace SRAM structures on processor chips with STT-RAM. However, a significant drawback of STT-RAM is its higher write latency and energy compared to SRAM. This dissertation first presents several approaches to use STT-RAM for future low-power processor designs across two different computing environments (high voltage and low voltage). Overall our target is to take advantage of the benefits of STT-RAM over SRAM to save power and at the same time try the best to accommodate STT-RAM's write drawbacks with novel solutions. In high voltage computing environment, we present a low-power microprocessor framework -- NVSleep, that leverages STT-RAM to implement rapid checkpoint/wakeup of idle cores to save power. In low voltage computing environment, we propose an architecture - Respin, that consolidates the private caches of near-threshold cores into unified L1 instruction/data caches that use STT-RAM to save leakage power and improve performance. On top of this shared L1 cache design, we further propose a novel hardware virtualization core management mechanism to increase resource efficiency and save energy. Although the non-volatility feature of non-volatile memories can be leveraged to build power-efficient designs, it also brings in security concerns as data stored in these memories will be persistent even after system power-off. In order to address this potential security issue, this dissertation deeply studies the vulnerabilities of non-volatile memory as processor caches when exposed to "cold boot" attacks and then proposes an effective software-based countermeasure to eliminate this security threat with reasonable performance overhead.

Committee:

Radu Teodorescu (Advisor); Feng Qin (Committee Member); Christopher Stewart (Committee Member); Yinqian Zhang (Committee Member)

Subjects:

Computer Engineering; Computer Science

Keywords:

Non-Volatile Memory, STT-RAM, Low-Power Processor Architecture, Cache, Near-Threshold Computing, Process Variation, Security, Secure Processor Design, Cold Boot Attack

Mahadevan Muralidharan, AnanthAnalysis of Garbage Collector Algorithms in Non-Volatile Memory Devices
Master of Science, The Ohio State University, 2013, Computer Science and Engineering
Non-volatile memory devices or flash, even with many advantages, still have a few problems such as the inability to update data in place. This necessitates the need for a garbage collector (GC) that can collect active data and create space by erasing flash blocks. However this is a very costly operation that increases the write latency thereby lowering the efficiency of the flash device. The frequency at which the GC is invoked by the underlying file system depends on the data’s traffic pattern as well as the fullness of the device. It is therefore important to study different GC algorithms for different traffic patterns and at varying fullness levels in order to find the most efficient one for a particular situation. In this report we study the efficiency of byte address non-volatile memory devices (such as NOR), under varying traffic patterns. We study the algorithms using simulations coded in Matlab. A simulator for the flash file system as well as the GC algorithms and various applications traffic was developed and used for the study. We compare and contrast the efficiency and the time taken for the GCs at utilization levels ranging from 2% to 98%. We also model some of the algorithms analytically and find that our analytical results match our simulations. The performance results for five different GC algorithms for flash devices for three traffic/access patterns are presented in this report. The access patterns include long-tailed, uniform and bimodal distributions. The algorithms studied are a round-robin style first in first out (FIFE), a greedy least active clean (LAC), 3-Generation (3-Gen) GC, N-Generation (N-Gen) GC (a generalized generation algorithm) and Eta-N-Generation (Eta-N-Gen) GC (a variation on N-Gen). The results indicate that round-robin style GC algorithm (FIFE) and greedy algorithm (LAC) perform better in most of the scenarios than generational algorithms. This is counter-intuitive to the existing norms. LAC slightly underperforms the FIFE under heavy flash utilization. For long-tailed traffic – the canonical use case for generational algorithms – FIFE and LAC still perform better than generational algorithms. The reason is that, it is non-trivial to configure a generational algorithm to get the optimum performance for a particular traffic pattern. To optimize performance, the radio of the size of subsequent generations should be the same as ratio between cold data and the rest of the data. Since in most application cases we do not know this a priori, static optimal configuration of generational algorithms is impossible. However an adaptive algorithm which changes allocations between generations on the fly could achieve better efficiency. Further we find that for better efficiency, at low levels of utilization it is important to isolate “cold’ data well, but at higher utilization identifying and handling hot data (i.e., never move the hot data) is important. Results from our study suggest that FIFE might work well for most of the application scenarios.

Committee:

Rajiv Ramnath (Advisor); Jayashree Ramanathan (Committee Member)

Subjects:

Computer Engineering; Computer Science

Keywords:

Garbage collection; Non-volatile memory device; Solid state device; statistical analysis; Uniform distribution; Pareto distribution; Bimodal distribution; Generational garbage collection; Greedy garbage collection; efficient garbage collection;