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Sun, XinyuFault Modeling and Fault Type Distinguishing Test Methods for Digital Microfluidics Chips
MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering
Physical defects in digital microfludics chips (DMCs) can be very complicated and extremely difficult to find precise models, because each defect may occur anywhere. In this thesis, we develop high-level abstract fault models based on investigating the faulty and fault-free behaviors of droplet moving. Two new fault models that were not found previously are proposed to enhance the reliability of DMCs. We believe that the high-level fault models can completely cover all defects involving two cells in a DMC array. Based on the new high-level fault models, we propose march algorithms (march-d and march-p/p+) to generate test patterns that can detect and distinguish fault types for each faulty digital microfludics chip. This is accomplished by merging both march-d and part of march-p without causing too much test length increase. These algorithms are implemented into a FPGA board attached to the simulated digital microfluidics chip such that built-in self-test can be accomplished without human intervention. We also develop an EDA tool and simulation platform for the proposed DMC-BIST system. Experimental results demonstrate that the proposed fault models, test and fault type distinguishing methods, built-in self-test circuit design, and emulation tool can effectively and efficiently achieve high quality test with minimal test cost.

Committee:

Wen Ben Jone, Ph.D. (Committee Chair); Xingguo Xiong, PhD (Committee Member); Ian Papautsky, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Fault modeling;Test methods;BIST;Digital microfluidics chip;Microfluidics EDA;March algorithm

MUKHERJEE, NANDINI3D DEFORMABLE CONTOUR SURFACE RECONSTRUCTION: AN OPTIMIZED ESTMATION METHOD
MS, University of Cincinnati, 2004, Engineering : Electrical Engineering
The object of this thesis is to develop an application for three-dimensional (3D) surface reconstruction from 3D point data. This development is to extend a particular newly derived 2D deformable contour extraction method to 3D surface reconstruction. Initially the functional flowchart is designed implementing the algorithm into task modules. Each task modules are coded and subsequently all the modules are put together to form the final software. The software package is developed using Microsoft Visual C++. Experiments were performed on test data, some mathematically generated and others obtained from MRI scan. The first set of mathematically generated 3D data consists of a 3D solid sphere of uniform gray scale value surrounded by a boundary of a different uniform grayscale value. The second set of mathematical data is a hollow cylinder of inner radius 5 and outer radius 15.The third set of data consists of 20 sequential slices of fat data from stomach obtained from MRI scans. In all cases the application tested favorably.

Committee:

Dr. William Wee (Advisor)

Keywords:

Image Segmentation; Region growing; Level Set; Fast March algorithm; 3D contour deformation; snakes

Coimbatore Raamanujan, SudarshanFault Modeling and Analysis of LP Mode FinFET SRAM Arrays
MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering
The need to keep up with Moore's law calls for high packing density in chips. Due to this very reason, IC fabrication industry is transforming from using conventional planar transistors to using 3D transistors, of which FinFET proves to be most viable because of its good short channel characteristics and ease of fabrication. Leakage power consumption has been a major concern considering the CMOS technology and it proves vital to reduce it. FinFETs, especially in LP mode provide design flexibility by controlling Vth to reduce leakage by trading off delay. In this research, we design an LP mode SRAM array and compare it with a similar SG mode design for performance, power and reliability. We then model all possible spot defects in HSPICE. We also discuss how leakage current could drastically increase due to resistive opens at back gates. In our results, we find one new fault model and we propose a march algorithm to detect all the fault behaviors found in our simulations.

Committee:

Wen Ben Jone, Ph.D. (Committee Chair); Carla Purdy, Ph.D. (Committee Member); Ranganadha Vemuri, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

FinFET LP mode;SG and LP mode comparison;Fault modeling;Read destructive coupling fault;Unique behavior at back gate;March algorithm

MARTIN, ROBERT ROHANMULTI-LEVEL CELL FLASH MEMORY FAULT TESTING AND DIAGNOSIS
MS, University of Cincinnati, 2005, Engineering : Computer Engineering
Single bit per cell flash memories have been widely used and many efficient testing and diagnosis methodologies have been proposed. On the other hand, their multi-level cell counterparts are relatively not well-known, even though they have many advantages such as low area, high-density, low power and short access times. To the best of our knowledge, no research papers have been published for MLC flash memory testing. One reason is that conventional march algorithms cannot be directly applied. Secondly, the faults affecting MLC are not formulated efficiently, and no theoretical analysis of such faults is available. This thesis is an attempt to bridge this gap by providing a simple solution to test and diagnose a MLC flash memory array. The fault model proposed takes into account many physical defects which cause the state of the memory cell to change. The diagonal flash test (FTX) and flash diagnosis (FDX) march algorithms proposed in this thesis are a first-of-its-kind for MLC flash. Their 100% fault coverage for the fault model we propose in this thesis, low complexity and test time make them an attractive methodology for testing and diagnosing faults for multi-level flash memories.

Committee:

Dr. Wen-Ben Jone (Advisor)

Keywords:

MLC; Multi-level Cell; Flash Memory; Fault Testing; Fault Diagnosis; Diagonal Algorithm; March Algorithm