Single bit per cell flash memories have been widely used and many efficient testing and diagnosis methodologies have been proposed. On the other hand, their multi-level cell counterparts are relatively not well-known, even though they have many advantages such as low area, high-density, low power and short access times. To the best of our knowledge, no research papers have been published for MLC flash memory testing. One reason is that conventional march algorithms cannot be directly applied. Secondly, the faults affecting MLC are not formulated efficiently, and no theoretical analysis of such faults is available. This thesis is an attempt to bridge this gap by providing a simple solution to test and diagnose a MLC flash memory array. The fault model proposed takes into account many physical defects which cause the state of the memory cell to change. The diagonal flash test (FTX) and flash diagnosis (FDX) march algorithms proposed in this thesis are a first-of-its-kind for MLC flash. Their 100% fault coverage for the fault model we propose in this thesis, low complexity and test time make them an attractive methodology for testing and diagnosing faults for multi-level flash memories.