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Sun, XinyuFault Modeling and Fault Type Distinguishing Test Methods for Digital Microfluidics Chips
MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering
Physical defects in digital microfludics chips (DMCs) can be very complicated and extremely difficult to find precise models, because each defect may occur anywhere. In this thesis, we develop high-level abstract fault models based on investigating the faulty and fault-free behaviors of droplet moving. Two new fault models that were not found previously are proposed to enhance the reliability of DMCs. We believe that the high-level fault models can completely cover all defects involving two cells in a DMC array. Based on the new high-level fault models, we propose march algorithms (march-d and march-p/p+) to generate test patterns that can detect and distinguish fault types for each faulty digital microfludics chip. This is accomplished by merging both march-d and part of march-p without causing too much test length increase. These algorithms are implemented into a FPGA board attached to the simulated digital microfluidics chip such that built-in self-test can be accomplished without human intervention. We also develop an EDA tool and simulation platform for the proposed DMC-BIST system. Experimental results demonstrate that the proposed fault models, test and fault type distinguishing methods, built-in self-test circuit design, and emulation tool can effectively and efficiently achieve high quality test with minimal test cost.

Committee:

Wen Ben Jone, Ph.D. (Committee Chair); Xingguo Xiong, PhD (Committee Member); Ian Papautsky, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Fault modeling;Test methods;BIST;Digital microfluidics chip;Microfluidics EDA;March algorithm

Coimbatore Raamanujan, SudarshanFault Modeling and Analysis of LP Mode FinFET SRAM Arrays
MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering
The need to keep up with Moore's law calls for high packing density in chips. Due to this very reason, IC fabrication industry is transforming from using conventional planar transistors to using 3D transistors, of which FinFET proves to be most viable because of its good short channel characteristics and ease of fabrication. Leakage power consumption has been a major concern considering the CMOS technology and it proves vital to reduce it. FinFETs, especially in LP mode provide design flexibility by controlling Vth to reduce leakage by trading off delay. In this research, we design an LP mode SRAM array and compare it with a similar SG mode design for performance, power and reliability. We then model all possible spot defects in HSPICE. We also discuss how leakage current could drastically increase due to resistive opens at back gates. In our results, we find one new fault model and we propose a march algorithm to detect all the fault behaviors found in our simulations.

Committee:

Wen Ben Jone, Ph.D. (Committee Chair); Carla Purdy, Ph.D. (Committee Member); Ranganadha Vemuri, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

FinFET LP mode;SG and LP mode comparison;Fault modeling;Read destructive coupling fault;Unique behavior at back gate;March algorithm

Kim, Hyoung-KookDefect-oriented fault analysis of a two-D-flip-flop synchronizer and test method for its application
PhD, University of Cincinnati, 2012, Engineering and Applied Science: Computer Science and Engineering
This thesis presents defect-oriented fault modeling and analysis of a two-D-flip-flop synchronizer and provides a test method for its application circuits. Bridging (open) defects are injected into any possible pair of internal nodes of the synchronizer. Then, HSPICE is used to perform the circuit analysis of each defect. The major purpose of this analysis is to acquire all possible faults that might occur in the synchronizer by each injected bridging (open) defect. Simulation results show that bridging and open defects can cause the synchronizer to generate stuck-at fault, functional timing fault, pulse output fault, one-time pulse fault, internal oscillation fault, and undefined output fault. Moreover, fault behaviors of the synchronizer depend on the location and resistance value of each defect, the input signal pattern (rising and falling), the input signal application time, and the applied clock frequency. The issues of fault behavior under the consideration of process variation, and the relationship between defects and the synchronizer failure mechanisms are also discussed. After dealing with failure analysis, an asynchronous First-In-First-Out (FIFO) interface (for multi-clock domain circuits) as an application of the two-D-flip-flop synchronizer is implemented. The number of synchronizers in the asynchronous FIFO interface depends on the width of the address lines. A general test method for the asynchronous FIFO interface is proposed. The proposed general test method evolves to the several test methods to detect the observed faults of all synchronizers in the asynchronous FIFO interface. Programmable delay generation and calibration are used to accomplish the pseudo at-speed delay testing for the FIFO circuit. Results demonstrate that the fault modeling and test methods developed in this research are effective, and can greatly enhance the reliability of a circuit which contains multiple clock domains.

Committee:

Wen Ben Jone, PhD (Committee Chair); Chien-In Henry Chen, PhD (Committee Member); Harold Carter, PhD (Committee Member); Carla Purdy, PhD (Committee Member); Philip Wilsey, PhD (Committee Member)

Subjects:

Computer Engineering

Keywords:

fault modeling;fault analysis;synchronizer;asynchronous FIFO;;;