This thesis presents defect-oriented fault modeling and analysis of a two-D-flip-flop synchronizer and
provides a test method for its application circuits. Bridging (open) defects are injected into any possible pair of internal nodes of the synchronizer. Then, HSPICE is used to perform the circuit analysis of each defect. The major purpose of this analysis is to acquire all possible faults that might occur in the synchronizer by each injected bridging (open) defect. Simulation results show that bridging and open defects can cause the synchronizer to generate stuck-at fault, functional timing fault, pulse output fault, one-time pulse fault, internal oscillation fault, and undefined output fault. Moreover, fault behaviors of the synchronizer depend on the location and resistance value of each defect, the input signal pattern (rising and falling), the input signal application time, and the applied clock frequency. The issues of fault behavior under the consideration of process variation, and the relationship between defects and the synchronizer failure mechanisms are also discussed. After dealing with failure analysis, an asynchronous First-In-First-Out (FIFO) interface (for multi-clock domain circuits) as an application of the two-D-flip-flop synchronizer is implemented. The number of synchronizers in the asynchronous FIFO interface depends on the width of the address lines. A general test method for the asynchronous FIFO interface is proposed. The proposed general test method evolves to the several test methods to detect the observed faults of all synchronizers in the asynchronous FIFO interface. Programmable delay generation and calibration are used to accomplish the pseudo at-speed delay testing for the FIFO circuit. Results demonstrate that the fault modeling and test methods developed in this research are effective, and can greatly enhance the reliability of a circuit which contains multiple clock domains.