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Han, QiangOn Resilient System Testing and Performance Binning
PhD, University of Cincinnati, 2015, Engineering and Applied Science: Computer Science and Engineering
By allowing timing errors to occur and recovering them on-line, resilient systems are designed to eliminate the frequency or voltage margin to improve circuit performance or reduce power consumption. With the existence of error detection and correction circuits, resilient systems bring about new timing constraints for path delay testing. With the characteristics of allowing timing errors to occur and recovering them on-line, the metrics of resilient system performance are different from traditional circuits, which results in new challenges on resilient system performance binning. Due to these new characteristics of resilient systems, it is essential to develop new testing and binning methodologies for them. In this research, we focus on resilient system testing and performance binning, and attempt to push forward the pace of resilient system commercialization. We make the following contributions. First, we propose a new DFT (design-for-testability) technique, which is able to deal with all different types of timing faults existing in resilient systems, and we develop an efficient test method based on binary search for error collection circuits. Then, a performance binning method based on structural at-speed delay testing is developed for resilient systems to greatly save the binning cost, and an adaptive clock configuration technique is proposed for yield improvement. Last but not least, we propose a new statistical performance analysis tool for resilient systems, called SERA (statistical error rate analysis), which takes process variations into consideration for error rate analysis and produces performance distribution function. With the help of SERA, we develop a profit-oriented binning methodology for resilient systems.

Committee:

Wen-Ben Jone, Ph.D. (Committee Chair); Chien-In Henry Chen, Ph.D. (Committee Member); Harold Carter, Ph.D. (Committee Member); Carla Purdy, Ph.D. (Committee Member); Ranganadha Vemuri, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Resilient computing;Delay testing;Performance binning;Yield improvement;Error rate modeling;Statistical analysis