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Obeidat, Nawar H.The Design and Development Process for Hardware/Software Embedded Systems: Example Systems and Tutorials
MS, University of Cincinnati, 2014, Engineering and Applied Science: Computer Engineering
Today embedded systems are found in all areas of our lives and have many different applications. They differ in their uses and properties as well as employing both software and hardware components in their implementations. This has made the design and development process for them much more complicated. Learning to use such a process is especially difficult for electrical engineering students, who have not been introduced to the systematic design and testing methodologies familiar to students trained in computer science and computer engineering. In this thesis, we illustrate the similarities and differences in the design and development design processes in for software systems and for software/hardware embedded systems. We give details for every stage for both types of systems and we develop detailed examples for example embedded systems, using a design process which extends the standard UML-based process used for software. In addition, we include details about project management. The examples and additional exercises and questions provide a set of tutorials which will assist students unfamiliar with complex design procedures in mastering the necessary skills to become well-trained embedded system developers.

Committee:

Carla Purdy, Ph.D. (Committee Chair); Raj Bhatnagar, Ph.D. (Committee Member); George Purdy, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Embedded Systems;UML based process;Design process;design and development process;hardware software embedded systems;vending machine

Leinweber, LawrenceImproved Cryptographic Processor Designs for Security in RFID and Other Ubiquitous Systems
Doctor of Philosophy, Case Western Reserve University, 2009, EECS - Computer Engineering
In order to provide security in ubiquitous, passively powered systems, especially RFID tags in the supply chain, improved asymmetric key cryptographic processors are presented, tested and compared with others from the literature. The proposed processors show a 12%-20% area and a 31%-45% time improvement. A secure protocol is also presented to minimize cryptographic effort and communication between tag and reader. A set of power management techniques is also presented to match processor performance to available power, resulting in greater range and responsiveness of RFID tags.

Committee:

Christos Papachristou, PhD (Committee Chair); Francis L. Merat, PhD (Committee Member); Swarup Bhunia, PhD (Committee Member); Xinmiao Zhang, PhD (Committee Member); Francis G. Wolff, PhD (Committee Member)

Subjects:

Computer Science; Electrical Engineering

Keywords:

Cryptography; elliptic curve cryptography; power management; RFID; embedded systems

Sikiligiri, Amjad Basha M.Buffer Overflow Attack and Prevention for Embedded Systems
MS, University of Cincinnati, 2011, Engineering and Applied Science: Computer Engineering

Embedded systems today play a significant role in all aspects of our lives ranging from critical medical applications to multi-purpose handheld devices to simple room temperature controls. Unfortunately, due to their ubiquity and characteristic features, embedded systems are prone to various security attacks. Software based security attacks, which target security loopholes in operating system and application software, are the most common security attacks because of their relatively easy and cost effective implementation.

Hence it's important for embedded system designers and application developers to have knowledge about existing security attacks so as to avoid them in their design. We survey various embedded system security attacks and present a detailed description for a class of software based security attacks, buffer overflow attack. We demonstrate a stack based buffer overflow attack using the Altera Nios II softcore processor and the Micrium MicroC/OS II RTOS kernel. We also present a method to prevent such an attack for this specific system. This method can be modified to apply to a wide range of embedded systems products

Committee:

Carla Purdy, PhD (Committee Chair); Yiming Hu, PhD (Committee Member); George Purdy, PhD (Committee Member)

Subjects:

Computer Engineering

Keywords:

Buffer overflow;Embedded systems

Ogallo, Godfrey G.Development of Remote Water Quality Monitoring System Using Disruption Tolerant Networking (DTN)
Master of Science (MS), Ohio University, 2016, Environmental Studies (Voinovich)
The efficiency of watershed management depends on the frequency of monitoring water quality. Remote water quality monitoring can improve watersheds management. However, this is often very costly and difficult to implement. This study focused on designing and building a low cost remote water quality monitoring system. This was achieved by integrating low cost computing technology, power management, monitoring sensors and `disruption tolerant networking’ (DTN). This system was used to measure water pH, electrical conductivity and temperature. The composite system is made up of three main components which includes the data acquisition node, communication module and the cloud database. The data acquisition node is made up of the sensor nodes which includes pH, conductivity and temperature sensors, credit-card sized computer and microcontroller. A side-by-side test between the low cost water quality monitoring system and a reference YSI 600 XLM sonde was conducted to demonstrate the effectiveness of the low cost system.

Committee:

Natalie Kruse (Advisor)

Subjects:

Communication; Environmental Management; Information Systems; Information Technology

Keywords:

DTN; Bundle Protocol; Embedded Systems; Remote water quality monitoring

Darr, Matthew JAdvanced embedded systems and sensor networks for animal environment monitoring
Doctor of Philosophy, The Ohio State University, 2007, Food, Agricultural, and Biological Engineering
Advancements in sensing and monitoring of air quality parameters within confined animal feeding operations have been realized through the application of embedded systems and advanced networking. The development of an embedded vibration sensor to detect the presence of ventilation fan activity provided researchers with an improved method to monitor ventilation from high capacity CAFO facilities. Experiments revealed over estimation errors common to the majority of passive ventilation sensors. Analysis of ventilation sensor systems resulted in proposed limits to overall measurement error by minimizing the modulus of fan on-time and sampling time. Controller Area Networks were found to be a viable means to link multiple analog and digital sensors through a multi-master based embedded network. It was found that signal attenuation was significant as bus lengths increased to a maximum of 600 meters. This attenuation was counteracted by reducing the baud rate of the communication and allowing for longer bit times. Signal reflection of the individual bits was another major factor of transmission error caused by the mismatch of impedance between the signal wire and the termination resistor. Wireless sensor networks were also evaluated for their potential to act as the data communication network within a multi-point sampling system inside a CAFO. Results from experimental path loss studies found many factors including antenna orientation, enclosure thickness, free space, antenna height, animal cages, and concrete floor separations to all be statistically relevant factors in determining the overall system path loss. It was further found that linear separation within an aisle and number of cage separations provided the highest levels of signal attenuation. A model was developed to predict the path loss at any point within a poultry layer facility based on the aisle and cage separation terms. The model was able to predict 86% of the system variability and was able to produce an average error of -0.7 dB for all combined points. The verification of all theoretical path loss models indicates that when applied to new systems not representative of poultry layer facilities, fundamental laws can be used to create initial predictions for path loss.

Committee:

Lingying Zhao (Advisor)

Subjects:

Engineering, Agricultural

Keywords:

Embedded systems; Microcontroller; Path loss; Mesh network; Confined animal feeding operation

Reddy, NitinDRIVER ASSISTANCE FOR ENHANCED ROAD SAFETY AND TRAFFIC MANAGEMENT
Master of Sciences, Case Western Reserve University, 2009, EECS - Computer Engineering
This study explores the use of inter vehicle communication to enhance road safety andtraffic management. A vehicle’s engine control unit (ECU) manages and controls various sensor signals, inputs and determines the output in terms of torque, fuel quantity and actuator positions. The data available in the ECU is however restricted only to that particular vehicle where it was generated. This work presents a scenario where critical data from each vehicle is broadcasted and a dynamic ad-hoc network of vehicles is formed. The algorithms in the ECU then detect possible collisions, decides which vehicle should take action and alerts the driver with the most optimum resolution. The analysis presented here is based on simulation data. Traffic management is achieved with modules placed along the road, which collect the broadcasted data. Modules, after analyzing traffic density and average speeds, interact with neighboring modules. This traffic information is broadcasted to all vehicles in close proximity to the traffic modules. The vehicle uses this information along with details from the navigation system to reroute the automobile to avoid high traffic areas.

Committee:

Christos Papachristou (Committee Chair); Francis Merat (Committee Member); Swarup Bhunia (Committee Member)

Subjects:

Computer Science

Keywords:

traffic management; collision avoidance; car safety; embedded systems; driver assistance;

McNichols, John M.Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
Master of Science (M.S.), University of Dayton, 2012, Electrical Engineering
Image compression standards continually strive to to achieve higher compression ratios while maintaining image quality. In addition to these goals, new applications require expanded features and flexibility as compared to existing compression standards. JPEG2000 is the latest in the line of image compression standards, offering higher compression ratios than its predecessor JPEG while maintaining comparable image quality. In addition, JPEG2000 offers an extended range of features including bit-rate control, region of interest coding and file-stream scalability with respect to resolution, image quality, components and spatial region. However, these additional features come with associated costs, primarily in the form of computational complexity. Due to the increased computational costs, JPEG2000 has not achieved the same wide-spread usage as JPEG. However, there are a number of specialized applications such as medical imaging and wide-area surveillance which demand the extended features offered by JPEG2000. These applications generally deal with high resolution imagery, resulting in extremely long encoding times when using consumer off the shelf platforms. As a result, many hardware implementations of the most computationally complex portions of JPEG2000, namely Tier I encoding, have been proposed. This thesis proposes using an embedded soft-core processor on a Field Programmable Gate Array (FPGA) for JPEG2000 code stream organization, known as Tier II. The soft-core processor chosen, Altera's NIOS II core, is coupled with existing Discrete Wavelet Transform (DWT) and Tier I implementations on a single FPGA to realize a fully embedded JPEG2000 encoder. Results show the feasibility of using an embedded soft-core processor on a FPGA to perform Tier II processing for JPEG2000.

Committee:

Eric Balster, PhD (Committee Chair); John Weber, PhD (Committee Member); Frank Scarpino, PhD (Committee Member)

Subjects:

Computer Engineering; Electrical Engineering

Keywords:

JPEG2000; NIOS II; Embedded processing; Embedded systems; System-on-chip; FPGA; Image processing; Image compression;

Duan, MinlanQuality of Service in Contour Guided Dissemination
Master of Science, University of Akron, 2007, Electrical Engineering
Recent advances offer novel devices that are integrated with limited, and yet effective, capabilities for computing and wireless communications over mesh topologies. While there are multiple paths between many pairs of nodes in such topologies, there are no methods that efficiently exploit all such paths. This thesis presents dissemination methods that exploit the multiple paths available between a pair of nodes in mesh topologies. By considering regular topology in which each node has eight neighbors, it is shown that the number of paths between a pair of nodes is limited by the relative locations of the nodes. A Contour is defined as the union of all shortest paths between a pair of nodes and its structure is characterized. It is shown that when messages are disseminated over the paths in a contour in a uniform manner, nodes along one path will always handle more messages than the nodes along other multiple paths. Optimal dissemination rules that ensure that all the nodes in a row, which is the set of nodes at the same distance from the source node, of a contour handle approximately the same number of messages. By modeling the multi-hop propagation in wireless mesh topology as a multi-stage queueing network, simulation results are presented to demonstrate the Quality of Service (QoS) achieved by the proposed optimal dissemination method. Although the results are based on regular topologies, they represent bounds on what could be achieved in general topologies. These results reveal that to achieve optimal dissemination, some nodes must disseminate the messages over the available paths and other nodes use only one of the available paths. Identifying these sets of nodes in general topologies is an interesting problem. In the future, the optimal dissemination techniques can be enhanced to improve QoS, mitigate interference, reduce hotspot effects, and to design next generation monitoring and surveillance systems based on wireless mesh topologies.

Committee:

Sastry Shiva (Advisor)

Keywords:

Quality of Service; Contour Guided Dissemination; Networked Embedded Systems; Uniform Spreading; Optimal Spreading; Mesh Topologies

McCartney, William P.Simplifying Embedded System Development through Whole-Program Compilers
Doctor of Engineering, Cleveland State University, 2011, Fenn College of Engineering
As embedded systems embrace ever more complicated microcontrollers, they present both new capability and new complexity. To simplify their development, some lessons of computer application development will translate with additional work. This thesis offers one such translation. It shows how whole-program compilers - those that broadly analyze a program's entire source code - can achieve performance gains and remove faults in embedded system applications. In so doing, this yields a novel stackless threading system named UnStacked C. UnStacked C enables cooperative multithreading without the risk of stack overflows in embedded system applications. We also propose a novel preemption system called Lazy Preemption. Unstacked C with Lazy Preemption enables stackless preemptive multithreading in embedded systems. These remove the possibility of thread stack overflows, but also significantly reduces the memory required for multithreading in embedded systems.

Committee:

Nigamanth Sridhar, PhD (Committee Chair); Yongjian Fu, PhD (Committee Member); Janche Sang, PhD (Committee Member); Dan Simon, PhD (Committee Member); Wenbing Zhao, PhD (Committee Member)

Subjects:

Computer Engineering; Computer Science; Electrical Engineering; Engineering

Keywords:

Stackless; Multithreading; Embedded Systems; Firmware; Compilers; C

Sundaresan, VijayArchitectural Synthesis Techniques for Design of Correct and Secure ICs
PhD, University of Cincinnati, 2008, Engineering : Computer Science and Engineering

Integrated Circuits (ICs) are widely used in all applications and industries like smart cards, cell phones, set-top boxes, automobiles, avionics, space exploration and bio-instrumentation, to name a few. Traditional IC design flows and architectural synthesis techniques have been developed primarily for area, power and performance optimization. In recent years, as we move into the nanometer semiconductor process era, the ability to integrate large and complex applications on a single semiconductor die coupled with the all pervasive nature of the technology and its impact on our daily lives, have brought into prominence two important IC optimization constraints: Security and Correctness.

In this thesis, we have developed novel architectural synthesis techniques at cell-level, circuit-level and algorithmic-level, in a hierarchical standard-cell-based IC design framework, to design correct and secure ICs. Formulation as a hierarchical framework allows efficient partitioning of the design problem into several clearly-defined design steps at various levels of abstractions, with a clear understanding of each design step and ability to incorporate the requirements of subsequent design steps. Furthermore, unlike naive security-centric IC design flows where security and IC implementation constraints (area, power and performance) are typically considered as orthogonal and often conflicting optimization goals, in this thesis, we developed a novel paradigm that could be used to simultaneously optimize security as well as IC implementation constraints (area and power), at various hierarchical levels of IC design. Together, these architectural synthesis techniques fit well in today's highly productive modular IC design flows, and thus efficiently design correct and secure ICs.

Committee:

Ranga Vemuri, PhD (Committee Chair); Jintai Ding, PhD (Committee Member); Karen Tomko, PhD (Committee Member); Harold Carter, PhD (Committee Member); Wen-Ben Jone, PhD (Committee Member)

Subjects:

Computer Science

Keywords:

Integrated Circuit Design; EDA; CAD for VLSI; Cryptographic Hardware Design; Secure Embedded Systems; Architectural Synthesis

Althaus, Joseph H.An Embedded Nonlinear Control Implementation for a Hovering Small Unmanned Aerial System
Master of Science (MS), Ohio University, 2010, Electrical Engineering (Engineering and Technology)
This thesis presents the design, development, and experimental verification of an embedded vehicle controller applied to a hovering small unmanned aerial system dubbed the UFO. The effort demonstrated the feasibility of implementation of advanced nonlinear controller designs in embedded hardware to achieve increased system performance. Furthermore, it was shown that the controller implementation was not penalized due to size, weight, and power build-up typically associated with vehicles in this class. Performance was verified experimentally through simulation case studies that subjected the vehicle and embedded controller to various real-world considerations. Finally, justification of approach occurred through analysis of the experimental results.

Committee:

J. Jim Zhu (Advisor)

Subjects:

Electrical Engineering; Engineering

Keywords:

VTOL aircraft; embedded systems; nonlinear control; flight controller; trajectory linearization

Jayaram, IndiraAdding non-traditional constraints to the embedded systems design process
MS, University of Cincinnati, 2011, Engineering and Applied Science: Computer Engineering
Embedded systems are ubiquitous and have a large number of applications. The requirements for embedded systems are not restricted to functionality but also include a lot of non-functional properties such as cost, reliability, safety, ease of use etc. This makes developing a standard design methodology for embedded systems challenging. In this thesis, we are attempting to include the non-traditional, non-functional constraints of embedded systems in the design process by weighting them in the order of their importance. We propose developing UML models for a system and annotating them with the non-functional constraints by using standard profile extensions and weighted constraint charts. We demonstrate the application of this design technique by developing a few example systems. One of the systems is implemented on Altera UP3 platform and demonstrates how the design technique leads us to choose the implementation that satisfies all the requirements, including the ones that are non-functional.

Committee:

Carla Purdy,, PhD (Committee Chair); Philip Wilsey, PhD (Committee Member); Xuefu Zhou, PhD (Committee Member)

Subjects:

Computer Engineering

Keywords:

Embedded systems;UML;MARTE

Naik, Vinayak ShashikantReliable and secure data transport in large scale wireless networks of embedded devices
Doctor of Philosophy, The Ohio State University, 2006, Computer and Information Science
Recent advances in semiconductor technology have resulted in techniques that can build miniaturized radios and sensor-actuators, which can be deployed in the physical world in a large scale. These inexpensive devices can be used to provide coordinated dense sensing, processing, and communicating. Combining these capabilities with robust system software will empower physical sciences with real-time data of high fidelity. To realize this opportunity, computer scientists must address new challenges posed for development of robust system software for the large scale resource constrained wireless networks of embedded devices (sensors). These devices have limited resources in terms of processing, memory, radio bandwidth, and energy. Further, once deployed these devices will necessarily remain untouched and expect to work for an extended period of time. All though Internet is a large scale network, all of the above mentioned constrained do not apply to the nodes in the Internet. Therefore, network services must be designed specifically for the large scale wireless sensor networks. The network services for large scale sensor network must have low time complexity and memory complexity. We provide low complexity reliable and secure data transport for large scale wireless networks of embedded devices. We focus on bulk data transport for two of the most commonly used services, viz. data dissemination and data collection. Our services are better than the state-of-the-art. We address the problem of key maintenance for providing secured communication in the presence of key compromise and denial-of-service attacks. We also investigate the use of testbed to facilitate experimentations for large scale wireless networks.

Committee:

Anish Arora (Advisor)

Subjects:

Computer Science

Keywords:

Network protocols; Real-time systems and embedded systems; Wireless; Wireless sensor networks; Computer security