The continual physical shrinking of semiconductor device dimensions is allowing for more integration between the previously segmented digital logic, memory, analog, and radio frequency domains – heralding the “More than Moore” era. Although able to meet the performance requirements for high-speed analog and RF, the devices are not guaranteed to always run at their typical sweet spot. The drifts from the optimal operation are due to many factors related to the silicon process and its response to changes in voltage and temperature, or what is collectively named PVT (Process, Voltage, Temperature) variations. These variations are a problem in all the integrated domains of the chip; however, RF circuits fail, in a more disproportionate manner, at sustaining proper operation over PVT. This makes them more prone to performance degradations and loss of yield when fabricated, in contrast to digital chips that can achieve near perfect yield. Putting both RF and digital together on a single chip, the hybrid system obviously inherits the lower yield, negating all the integration advantages. Therefore, the RF portions, in a sense, represent the SoC’s Achilles’ heel; in essence, an overly powerful and densely integrated chip can be made useless by a smaller underperforming portion of the chip.
The ultimate goal is to increase the yield of the RF blocks by actively maintaining them in their optimal operating region. This proves to be a non-trivial task, as the operating conditions of the system at all times need to be known. For complex integrated systems, full verification during fabrication testing is quite prohibitive, in time and cost. A solution would be to build self-testing, and eventually self-healing, systems. Built-in-Self-Test (BiST) paradigms have already established themselves in the validation of digital blocks but are now becoming an increasingly active domain of research and development in RF. The notion of migrating RF test functionality to inside the chip brings us one step closer to cognitive-like radios. If RF blocks and systems can test for, and extract, their performance, then the ability to calibrate and cancel discrepancies can also be built into the system. Hence, Built-in-Self-Calibration (BiSC) can be layered on top of BiST to result in auto-correcting RF impairments at the block and system levels.
In this dissertation, we discuss the problems set forth by increased integration and decreased circuit robustness. We also express the requirements for building efficient true self-test mechanisms using on-chip resources not only as value-added elements but also as necessary components for successful first-pass success of RF SoCs. An efficient RF sensor is presented along with the different possible built-in-tests for which it can be employed. The implementation of these on-chip test strategies aid in the development of calibration techniques that leverage the strengths of the more robust parts of the system to cover up the weaknesses of the others.