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Sun, XinyuFault Modeling and Fault Type Distinguishing Test Methods for Digital Microfluidics Chips
MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering
Physical defects in digital microfludics chips (DMCs) can be very complicated and extremely difficult to find precise models, because each defect may occur anywhere. In this thesis, we develop high-level abstract fault models based on investigating the faulty and fault-free behaviors of droplet moving. Two new fault models that were not found previously are proposed to enhance the reliability of DMCs. We believe that the high-level fault models can completely cover all defects involving two cells in a DMC array. Based on the new high-level fault models, we propose march algorithms (march-d and march-p/p+) to generate test patterns that can detect and distinguish fault types for each faulty digital microfludics chip. This is accomplished by merging both march-d and part of march-p without causing too much test length increase. These algorithms are implemented into a FPGA board attached to the simulated digital microfluidics chip such that built-in self-test can be accomplished without human intervention. We also develop an EDA tool and simulation platform for the proposed DMC-BIST system. Experimental results demonstrate that the proposed fault models, test and fault type distinguishing methods, built-in self-test circuit design, and emulation tool can effectively and efficiently achieve high quality test with minimal test cost.

Committee:

Wen Ben Jone, Ph.D. (Committee Chair); Xingguo Xiong, PhD (Committee Member); Ian Papautsky, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Fault modeling;Test methods;BIST;Digital microfluidics chip;Microfluidics EDA;March algorithm

Soomro, Rahman AbdulTestability insertion in bit-slice data path designs: A pseudo-exhaustive BIST approach
Doctor of Philosophy, Case Western Reserve University, 1994, Computer Engineering
Partition and test has been a time-saving method for exhaustive testing. I present a bit-sliced approach for exhaustive testing at system speed. The objective of this research is not to design a system, but to make the system testable. A method is introduced for producing exhaustive test patterns using LFSR-C (Linear Feedback Shift Register Counter) as a test pattern generator (TPG) for a two port ALU using a one phase clock. The scheme called Run-n-Hold scheme, generates test patterns at clock speed; in other words, the transitivity of test patterns is relatively high. Once the testing scheme is developed, test resource optimization is of much concern. Test resources consist of a test pattern generator and signature analyzer – LFSR-C and MISR (Multi-Input Signature Register). A bypass method is exploited for propagating test patterns to the ALU and response verification to the MISR. In this scheme, those ALUs and/or registers not in use during testing are used as bridges to pass the test patterns to the ALU under test and/or the test response to the designated MISR. If one ALU is used between test resource and the ALU under test, we call it one level, or one bypass. Serial testing is exploited in this research, which means one ALU is tested at a time. We have considered three ALU tes ting sequences: (1) random method: in this method the ALU sequence is arranged in a random order, then testing is conducted; (2) straight forward method: in this method the ALU sequence is arranged in a straight forward way; (3) hill climbing method: in this scheme the ALU test sequence is obtained by the well known hill climbing method. This method can be described briefly as follows: select an ALU to begin with, add another ALU to the sequence such that sequential combination of both ALUs gives a minimum area overhead; add another ALU until all ALUs are in the sequence. We selected the first ALU in random fashion and then added other ALUs according to the procedure described above. This selection did not give us the expected results. Alternatively, we started with the ALU whose input registers are connected to maximum number of ALUs in the data path. In the system testing mode the data buss is used for test pattern propagation, the system bus is used for response transmission to the designated MISR in the case of bypassing, and the system control bus is used for the test control. Finally, this test scheme is developed such that random testing can be accomplished with the same technique used for exhaustive testing; and exhaustive test controller can be used as the random test controller. (Abstract shortened by UMI.

Committee:

Christos Papachristou (Advisor)

Subjects:

Computer Science

Keywords:

Testability insertion bit-slice data path designs pseudo-exhaustive BIST approach

Gadde, PriyankaA BIST Architecture for Testing LUTs in a Virtex-4 FPGA
Master of Science in Electrical Engineering, University of Toledo, 2013, College of Engineering
Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement a given digital design. Built-In Self-Test (BIST) is a testing technique that enables the device to test itself without the need for any external test equipment. The re-programmability feature of the FPGAs makes BIST a favorable approach for testing FPGAs because it eliminates any area or performance degradation associated with BIST. In order to ensure proper operation of Look up Tables in Xilinx Virtex-4 Field-Programmable Gate Arrays (FPGAs), a dependable and resource efficient test technique is needed so that the functional operation of the memory can be tested. Traditional BIST techniques for FPGAs suffer from a large number of logic resource requirements and long test times in the implementation and testing of the circuit. The work presented in this research simplifies the BIST architecture and reduces the test time required to test the Look up Tables in a Virtex-4 FPGA. The proposed technique is capable of testing the following types of memory faults: stuck-at fault, transition fault, address decoder fault, incorrect read fault, read destructive fault, deceptive read destructive fault, data retention fault, state coupling fault, transition coupling fault, incorrect read coupling fault, read destructive coupling fault, and deceptive read destructive coupling fault in a SRAM based FPGA.

Committee:

Niamat Mohammed (Advisor); Alam Mansoor (Committee Member); Sun Weiqing (Committee Member)

Subjects:

Electrical Engineering

Keywords:

BIST; SRAM; Faults; Memory; Virtex-4 FPGA; Read Faults; Write Faults; Built in Self-Test

Poling, BrianOn-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test
Master of Science in Engineering (MSEgr), Wright State University, 2007, Electrical Engineering
Poling, Brian S. M.S. Egr., Department of Electrical Engineering, Wright State University, 2007. On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In Self-Test. Built-In Self-Test (BIST) is a method of designing and creating an electronic chip or an electronic system that can self test for correct functionality and ensure no manufacturing defects. The reason for analog BIST is the testing of analog parts of analog and mixed-signal ICs is a costly process that traditionally requires the use of expensive high-end automatic test equipment. Due to the nature of the testing and length of the testing process, an efficient analog BIST scheme is in high demand for the ever increasing complexity of analog and mixed-signal circuits. This thesis presents a BIST scheme for generation and response waveform extraction that allows the detection of a faulty circuit design. Along with the detection, an approach to test high speed analog and mixed-signal circuits with test signals upwards of 1GHz is presented. A practical application is to test analog or mixed-signal IC that has a wide bandwidth ADC in its front-end. The BIST scheme includes a method to store the test signal and generate it for the circuit to be tested along with a way to extract the response test signal from multiple test points and allow fault detection. Along with this research, a stepping stone is implemented for analog modeling using MATLAB for accuracy and speed of circuit simulations. The problems associated with the BIST scheme and analog modeling is discussed, along with recommendations.

Committee:

Henry Chen (Advisor)

Keywords:

Buffer Design; BIST; ANALOG; 1GHz; DAC; ADC; Final Buffer

XIONG, XINGGUOBUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES
PhD, University of Cincinnati, 2005, Engineering : Computer Engineering
With the rapid development of MEMS (microelectromechanical system) and its increasing applications to safety-critical applications, MEMS testing and fault-tolerant MEMS design are becoming more and more important. A robust and efficient MEMS testing solution is in urgent need for MEMS commercialization, and yield and reliability are also very important issues for MEMS devices. In this thesis both built-in self-test (BIST) and built-in self-repair (BISR) of capacitive MEMS devices are studied. First, we propose a dual-mode built-in self-test (BIST) technique for capacitive MEMS devices. The BIST technique partitions the fixed (instead of movable) capacitance plates. Due to this partition, the BIST technique can be extended to bulk micromachining and other MEMS technologies. Based on the partition, both sensitivity and symmetry BIST modes can be implemented. Since each of both modes has its own fault coverage, a combination of them ensures a more robust test solution. Based on the dual-mode BIST technique, a built-in self-repair (BISR) technique for comb accelerometer devices is proposed. The device consists of several identical modules. Among them, some are connected as the main device, while others act as redundancy. If any of the working modules is found faulty during BIST, the control circuit will replace it with a good module. In this way, the device can be self-repaired. Electrostatic force can also be used as a powerful tool to compensate the sensitivity loss due to modularized design. The BISR scheme leads to great improvement in device yield as well as its reliability. In order to evaluate the effectiveness of the BISR scheme on yield improvement, a yield model for MEMS redundancy repair is developed. The result demonstrates that a significant yield increase can be achieved for moderate initial yield. The control circuit for the BISR implementation is also discussed. In order to evaluate the reliability enhancement due to redundancy repair, a MEMS reliability model is also developed. Based on the reliability model, we evaluate the MEMS reliability in three different failure mechanisms: fatigue, shock and stiction. Analysis results prove that the BISR design leads to effective reliability enhancement for various failure mechanisms.

Committee:

Dr. Wen-Ben Jone (Advisor)

Keywords:

Microelectromechanical System (MEMS); Built-in Self-test (BIST); Built-in Self-repair (BISR); Yield Analysis; Reliability

Liu, JianxunPseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects
PhD, University of Cincinnati, 2011, Engineering and Applied Science: Computer Science and Engineering
As technology approaches deep sub-micron and clock frequency approaches Giga Hertz, the signal integrity problem of high-speed interconnects is becoming a more and more serious issue. In this work, we propose a pseudo-exhaustive testing scheme for signal integrity faults of high-speed SoC interconnects. We first validate the applicability of traditional pseudo-exhaustive testing methods to high-speed interconnect testing by validating the crosstalk locality. Base on the concept of crosstalk locality, a PE-BIST testing scheme for simple interconnect bus structures is proposed. The scheme uses a serial scan chain interface, and thus can be easily integrated with existing boundary scan architectures. Special boundary scan cells and instructions to support such integration are also discussed. The proposed PE-BIST method is then extended to arbitrary interconnect structures. With the aid of a Net Interference Graph (NIG), we can easily identify the PE-BIST test cone size and assign individual nets into PE-BIST channels. The test architecture for arbitrary interconnects is also very simple, largely reusing existing BIST components built on the chip. The hardware overhead can therefore be minimized. In order to control the test cone size for PE-BIST, shield canbe inserted into the interconnect structure to control the test time. We also present a post global routing track placement method to reduce shielding overhead. Simulation results show that the interconnect signal integrity problem can be dealt with by PE-BIST with minimum shielding overhead and reasonable test time. Finally, PE-BIST uses a parallel testing scheme and excites many aggressor nets to do the transitions which may lead to excessive power dissipation during testing. Power limit is usually considered in current SoC design, and thus the power dissipation for PE-BIST cannot be negligible. We use an efficient high level power modeling scheme to partition a PE-BIST solution into small child PE-BIST solutions so that each child PE-BIST solution can be tested within a given test power limit.

Committee:

Wen Ben Jone, PhD (Committee Chair); Chien-In Henry Chen, PhD (Committee Member); Harold Carter, PhD (Committee Member); Carla Purdy, PhD (Committee Member); Ranganadha Vemuri, PhD (Committee Member)

Subjects:

Computer Engineering

Keywords:

Interconnect Testing;Pseudo-Exhaustive Testing;PE-BIST;Signal Integrity;SoC;High Speed Interconnect

Akour, Amneh M.Design Techniques for Manufacturable 60GHz CMOS LNAs
Doctor of Philosophy, The Ohio State University, 2011, Electrical and Computer Engineering
Emerging broadband applications are pushing for the need to build high data rate wireless transceivers at 60GHz for high volume low cost mobile devices. Central to the success of implementing such transceivers is the robust design of 60GHz CMOS RF front ends, especially the low noise amplifiers (LNAs). In the future, CMOS technology is expected to enable low-cost mm-wave applications such as high data-rate communication links, passive and active imaging and sensor systems, and instrumentation and measurements equipment. Building highly integrated inexpensive mm-wave CMOS devices requires high quality factor lumped and distributed passives with accurate and scalable transistor and passives models. My research work focuses on demonstrating a methodology for generating a scalable compact model for on-chip transmission lines and interconnects on lossy silicon substrate. The model is demonstrated over 20-60 GHz frequency band using two types of transmission lines built in TSMC’s 0.18 µm CMOS technology. Several CPWs and Microstrip lines are designed with different lengths to verify the accuracy and scalability of the extracted model. The compact model shows an excellent agreement with measured data with maximum deviation in S11 magnitude and phase of 9.2% and 5.6%, respectively, and maximum deviation in S21 magnitude and phase of 10.1% and 6.6%, respectively. Compared to existing model extraction methodologies, the required time for generating the compact model and simulating transmission lines is reduced significantly. The generated models are fully compatible with all commercial circuit simulators. This work presents key design techniques for different CMOS mm-wave LNA topologies. The proposed LNA topologies are, the three-stage cascode RF NMOS configuration and four-stage Common Gate followed by Common Source configuration. Simulation results for 60GHz LNAs show that the first topology can achieve a peak gain of 16.67 dB with a 3-dB bandwidth of 7 GHz, and a noise figure less than 11.04 dB over the entire bandwidth. The achieved peak gain from the second topology is 9.7 dB with a 3-dB bandwidth of 7 GHz and a noise figure less than 13.06 dB over the entire bandwidth. Simulation results for Sub-THz LNAs show that the first topology can achieve a peak gain of 23.5 dB at 92.1 GHz with a 3-dB bandwidth of 25 GHz, and a noise figure less than 5.5 dB over the entire bandwidth. The achieved peak gain from the second topology is 23.2 dB at 105 GHz with a 3-dB bandwidth of 15 GHz and a noise figure less than 6.1 dB over the entire bandwidth. The LNAs are designed and tested in 90nm RF CMOS. Moreover in today’s radio design environment, the front-end analog devices in the transceiver require several silicon spins before they meet the specifications and they have relatively low yields. My work aims to propose a digital self-calibration technique for LNAs’ to enhance the yield to at least 90%. The proposed technique is shown to maintain typical specified performance at worst case corners in the presence of random process, supply and temperature variations, and hence allowing for manufacturable 60GHz RF CMOS design for high volume applications without leading to over-design or increasing power consumption.

Committee:

Mohammed El-Naggar, PhD (Advisor); Waleed Khalil, PhD (Advisor); Patrick Roblin, PhD (Committee Member); Donald Houser, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

mm-wave Radios; LNA; Built-In Self-Test (BIST) CAlibration; Yield; Transmission Line; Compact mdel; Interconnects

Bou Sleiman, SleimanBuilt-in-Self-Test and Digital Self-Calibration for Radio Frequency Integrated Circuits
Doctor of Philosophy, The Ohio State University, 2011, Electrical and Computer Engineering
The continual physical shrinking of semiconductor device dimensions is allowing for more integration between the previously segmented digital logic, memory, analog, and radio frequency domains – heralding the “More than Moore” era. Although able to meet the performance requirements for high-speed analog and RF, the devices are not guaranteed to always run at their typical sweet spot. The drifts from the optimal operation are due to many factors related to the silicon process and its response to changes in voltage and temperature, or what is collectively named PVT (Process, Voltage, Temperature) variations. These variations are a problem in all the integrated domains of the chip; however, RF circuits fail, in a more disproportionate manner, at sustaining proper operation over PVT. This makes them more prone to performance degradations and loss of yield when fabricated, in contrast to digital chips that can achieve near perfect yield. Putting both RF and digital together on a single chip, the hybrid system obviously inherits the lower yield, negating all the integration advantages. Therefore, the RF portions, in a sense, represent the SoC’s Achilles’ heel; in essence, an overly powerful and densely integrated chip can be made useless by a smaller underperforming portion of the chip. The ultimate goal is to increase the yield of the RF blocks by actively maintaining them in their optimal operating region. This proves to be a non-trivial task, as the operating conditions of the system at all times need to be known. For complex integrated systems, full verification during fabrication testing is quite prohibitive, in time and cost. A solution would be to build self-testing, and eventually self-healing, systems. Built-in-Self-Test (BiST) paradigms have already established themselves in the validation of digital blocks but are now becoming an increasingly active domain of research and development in RF. The notion of migrating RF test functionality to inside the chip brings us one step closer to cognitive-like radios. If RF blocks and systems can test for, and extract, their performance, then the ability to calibrate and cancel discrepancies can also be built into the system. Hence, Built-in-Self-Calibration (BiSC) can be layered on top of BiST to result in auto-correcting RF impairments at the block and system levels. In this dissertation, we discuss the problems set forth by increased integration and decreased circuit robustness. We also express the requirements for building efficient true self-test mechanisms using on-chip resources not only as value-added elements but also as necessary components for successful first-pass success of RF SoCs. An efficient RF sensor is presented along with the different possible built-in-tests for which it can be employed. The implementation of these on-chip test strategies aid in the development of calibration techniques that leverage the strengths of the more robust parts of the system to cover up the weaknesses of the others.

Committee:

Mohammed Ismail El-Naggar, PhD (Advisor); Waleed Khalil, PhD (Committee Member); Patrick Roblin, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

RFIC;BiST;self-calibration;self-healing;Integrated Circuits;robustness;yield