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HANDA, MANISHMACRO BASED COMPILER FOR A PARTIALLY RECONFIGURABLE COMPUTER
MS, University of Cincinnati, 2002, Engineering : Computer Engineering
This research focuses on the software architecture of a reconfigurable computer (RC). Reconfigurable computers consist of field-programmable gate arrays (FPGAs). An application task for a reconfigurable computer is typically specified in a hardware description language such as VHDL or Verilog. This task can be divided into small independent subtasks, which, if executed in a specific order, will result in the completion of the task. In a typical application, the task in its entirety cannot be mapped onto a single FPGA due to the area limitations. The subtasks are small enough to individually fit into the FPGA device. The same FPGA can be reprogrammed many times to perform each of the subtasks. Thus a large task can be executed on a small FPGA. In this research, a self-contained set of CAD tools is developed for compiling a task onto a partially reconfigurable computer. Using the compiler developed in this research, starting from the register-transfer level (RTL) description of the task, partial bit-streams for the Xilinx Virtex FPGA can be generated. These bit-stream files can be used to reconfigure the partially reconfigurable processor to execute the task. High level synthesis is performed on the algorithmic specifications give in VHDL of the task to obtain the RTL description. The RTL description is composed of small sequential blocks called Basic Blocks. Data path synthesis is performed and a controller is generated for each basic block during high-level synthesis. A macro based synthesis approach is used for the synthesis of the data path. This approach eliminates the need for the time-consuming logic synthesis process. The macros used for implementation of the task are part of a pre-designed library based on the Xilinx JBits. The macros are implemented as Java classes. These macros are run-time parameterizable. A controller, along with combinational decoders, is used to control the data flow throw data path. The macros in data path and controller are placed and routed and finally, partial bit-streams are generated which can be used to configure the reconfigurable processor. Partial reconfiguration is used for the propagation of intermediate result of the subtasks via register macros on the chip. A host controller program is written to control execution of task on the reconfigurable computer. A set of benchmark tasks, written in VHDL, is implemented on the reconfigurable computer. The partial reconfiguration scheme is shown to be effective in reducing the reconfiguration time. Further, the macro based methodology is shown to be effective in reducing the compilation time.

Committee:

Dr. Ranga R. Vemuri (Advisor)

Keywords:

partial reconfiguration; dynamic reconfiguration; Field Programmable Gate Array (FPGA); synthesis

NOLL, MICHAEL PAULVERTICAL LIFE: RECONFIGURED
MARCH, University of Cincinnati, 2003, Design, Architecture, Art, and Planning : Architecture
Urban sprawl has caused a severe depletion of activity and community in the Central Business Districts of many Midwestern cities in the United States. This change is the result of fifty years of political and social shifts beginning with the Federal Housing Act and the Federal Interstate Highway Program and continuing today as digitization shrinks the spatial requirements of many information-based corporations and sends their workers to the suburbs. The goal of this thesis is to use the current CBD infrastructure to bring a sense of community life back to the spaces of the city center. The design portion of the thesis reconfigures Fifth Third Tower on Fountain Square in the CBD of Cincinnati, Ohio. A better understanding of the future of the CBD and the way in which the buildings that make up this zone can be modified will be the prime benefit of the research and design.

Committee:

Michael McInturf (Advisor)

Subjects:

Architecture

Keywords:

central business district; sprawl; tall building; reconfiguration; architecture

LEE, TAI-CHUNAN EVENT-BASED APPROACH TO DEMAND-DRIVEN DYNAMIC RECONFIGURABLE COMPUTING
MS, University of Cincinnati, 2001, Engineering : Computer Engineering
A Reconfigurable Computer (RC) has the ability to modify its internal structure by applying specific system configurations so that it can be well suited to handle different computational tasks. It deviates from traditional computing platforms by having both good application flexibility and performance. A Demand-driven Dynamic Reconfigurable Computer (DDRC) belongs to the subset of RC that performs local run-time reconfiguration and reacts dynamically to different computing demands. A DDRC system does not rely on a pre-defined execution schedule as its reconfiguration reference. Instead, the data type that the system encounters or the functionality that the system is required to provide determines the reference. A controller mechanism is therefore needed to handle the demand processing and to generate configurations dynamically for the system. Although it has the potential for achieving not only faster performance but also higher resource utilization rate, the DDRC system suffers from a large penalty on implementation design due to increased complexity. In this thesis we introduce a new approach, of which an event-based controller is used for a modular architecture, in order to simplify the designing issues for implementing DDRC systems. First, a generic model of Field Programmable Gate Array (FPGA) device is defined as well as the module and routing resource structure. Based on this model, the proposed controller will handle six different basic events, of which the most important one is the Add Module event that acts as the system constructor by placing new modules onto the FPGA chip. Three algorithms for module placement are introduced and their performance is compared by software simulation results. A simple but fast and memory-conservative router is also introduced to handle dynamic connection routing and its performance is studied through software simulation. In conclusion the proposed controller provides a well-defined lower level run-time placement and routing mechanism so that high level system functions can be more easily built upon this architecture.

Committee:

Dr. Harold W. Carter (Advisor)

Keywords:

FPGA; dynamic reconfiguration; demand-driven

PANDEY, ANKURA MULTITHREADED RUNTIME SUPPORT ENVIRONMENT FOR DYNAMIC RECONFIGURABLE COMPUTING
MS, University of Cincinnati, 2002, Engineering : Computer Engineering
Reconfigurable computing system containing a number of reconfigurable devices is designed to reconfigure some or all of the devices during execution. An important aspect of reconfigurable computing is to develop tools that aid designer in mapping algorithms and computational tasks to the adaptive system. In this thesis we propose a runtime multithreaded support environment for managing the loading, execution and swapping of application modules on a FPGA. A virtual hardware manager is created that schedules execution of application modules, allocates and de-allocates FPGA resources. A fast runtime placement algorithm is proposed and evaluated for the system. Issues involving data storage are investigated. The impact of multithreading and pre-fetching is summarized. We have also suggested a component-based approach to application design. The performance of proposed a runtime system incorporating these algorithms was evaluated in a simulator based environment and is described here.

Committee:

Dr. Harol W. Carter (Advisor)

Keywords:

reconfigurable computing; runtime reconfiguration; runtime support environment; OS for FPGA

Ding, FeiSmart Distribution System Automation: Network Reconfiguration and Energy Management
Doctor of Philosophy, Case Western Reserve University, 2015, EECS - Electrical Engineering
Smart distribution system automation is the key to realizing a highly reconfigurable, reliable, flexible and active distribution system. Automated network reconfiguration including restoration is the most studied area in distribution automation, and it contributes to power loss minimization, voltage improvement and also can enable the distribution network to respond to contingencies and changes happened in the grid. Distributed energy resources at the customer premises, energy storage systems and plug-in electric vehicles are indispensable parts of future smart distribution systems. Their participations have brought more dynamics and uncertainties into the grid, and hence new technologies at both planning and operation levels must be developed to manage the energy dispatched from distributed energy resources and energy storage units, the charging and discharging behaviors of electric vehicles so that the entire power distribution system could operate stably and efficiently. Meantime, due to the intermittent, imperfectly predicted renewable energy and more complicated, uncertain load patterns, two challenges have arisen on network reconfiguration study, including more frequent reconfiguration actions and more complicated optimization problems for determining the optimal network topology. Thus, new approaches for reconfiguring distribution networks must be developed to overcome these challenges. In order to address the above challenges which distribution systems are facing to and develop new technologies for realizing smart distribution automation, a comprehensive study on network reconfiguration and energy management of distributed generation systems was studied. The contributions of this dissertation include: (1) proposed a novel problem formulation for network reconfiguration problem based on “switch states”; (2) developed three new methods to solve the optimization problem including heuristic algorithm, hybrid algorithm and revised genetic algorithm; (3) proposed a hierarchical, decentralized network reconfiguration approach that has been proved to have significant computational advantage compared with other existing methods; (4) proposed the concept of “dynamic network reconfiguration” in which the impact of time-varying load demands, renewable energy generation and other contingencies on the optimal distribution network topology were fully addressed and analyzed. (5) Since DG has become one of the most important parts in distribution systems. The mechanism of distributed generation itself and the impact of distributed generation on distribution system analysis must be studied. This dissertation has studied the modeling and reactive control of multiple DG systems, and also studied the unbalanced distribution feeder reconfiguration and proposed energy management strategy for controlling all grid-connected DGs in order to optimize distribution system operation.

Committee:

Kenneth Loparo (Advisor); Vira Chankong (Committee Member); Hong Mingguo (Committee Member); Prica Marija (Committee Member)

Subjects:

Electrical Engineering; Energy

Keywords:

Smart Distribution System, Distribution Automation, Network Reconfiguration, Energy Management, Distributed Generation

Morell, Jared AnthonyAdaptive Resizing of Deadline-Driven Requests for Provisioning Traffic in Elastic Optical Networks
Master of Science, Miami University, 2013, Computational Science and Engineering
Spectrum-sliced elastic optical networks, enabled by technological advances such as CO-OFDM, bandwidth-variable transponders, bandwidth-variable optical cross-connects, and optical multi-level modulation, provide a means to divide the spectrum of light transmitted over optical fibers on a finer granularity than WDM and to slice-off just the adequate amount for each connection. It is envisioned that these networks will carry various types of traffic with different service level guarantees, including Deadline-Driven Requests (DDRs) that require the data to be transferred by a given deadline without imposing a specific constant bandwidth requirement. As a result, DDRs can be provisioned with variable transmission rates between their arrival times and deadlines. For this thesis, the connection-request-provisioning problem is considered in a reconfigurable elastic optical network that supports such bandwidth readjustments on DDRs through minimal reconfigurations within the network. Various distance-adaptive routing, spectrum assignment and reconfiguration algorithms are developed for this purpose.

Committee:

Gokhan Sahin (Advisor); Donald Ucci (Committee Member); Chi-Hao Cheng (Committee Member)

Subjects:

Computer Engineering; Computer Science

Keywords:

Deadline-driven traffic; network reconfiguration; elastic networks; software-defined networks; bandwidth resizing; SLICE

Zhao, YueAutomatic Prevention and Recovery of Aircraft Loss-of-Control by a Hybrid Control Approach
Doctor of Philosophy (PhD), Ohio University, 2016, Electrical Engineering & Computer Science (Engineering and Technology)
In this dissertation, an integrated automatic flight controller for fixed-wing aircraft Loss-of-Control (LOC) Prevention and Recovery (iLOCPR) is designed. The iLOCPR system comprises: (i) a baseline flight controller for six degrees-of-freedom (6DOF) trajectory tracking for nominal flight designed by trajectory linearization, (ii) a bandwidth adaption augmentation to the baseline controller for LOC prevention using the timevarying PD-eigenvalues to trade tracking performance for increased stability margin and robustness in the presence of LOC-prone flight conditions, (iii) a controller reconfiguration for LOC arrest by switching from the trajectory tracking task to the aerodynamic angle tracking in order to recover and maintain healthy flight conditions at the cost of temporarily abandoning the mission trajectory, (iv) a guidance trajectory designer for mission restoration after the successful arrest of a LOC upset, and (v) a supervisory discrete-eventdriven Automatic Flight Management System (AFMS) to autonomously coordinate the control modes (i) - (iv). Theoretical analysis and simulation results are shown for the effectiveness of the proposed methods.

Committee:

Jim Zhu (Advisor); Douglas Lawrence (Committee Member); Frank Van Grass (Committee Member); Robert Williams (Committee Member); Aili Guo (Committee Member); Sergiu Aizicovici (Committee Member)

Subjects:

Aerospace Engineering; Engineering

Keywords:

Aircraft Loss-of-control; hybrid; arrest; prevention; recovery; flight control system; arrest; guidance; trajectory linearization control; switching mode; reconfiguration; bandwidth adaptation; multiple-time-scale nested loop

DASASATHYAN, SRINIVASANSYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs
MS, University of Cincinnati, 2001, Engineering : Computer Engineering
Partially reconfigurable devices have the ability to configure a portion of the device while the remaining portion of the device is still operational. This feature can be used to improve the performance of a pipelined design by overlapping the reconfiguration of a stage with the execution of previous stages. The above technique is called pipeline reconfiguration. By configuring pipeline stages one every clock cycle the constraint on the design size can be eliminated.This technique virtualizes the hardware and allows designs of any size to execute on finite sized devices. Virtual Pipelining uses pipeline reconfiguration and hardware virtualization to improve the performance of the design. This thesis presents a design flow for automatically synthesizing Virtual Pipelines on Virtex based FPGAs in order to improve the performance of a pipelined design. The input specification is a data flow graph with various arithmetic and logic operations. The input pipelined specification is split into a number of partial designs, each representing the status of the device during every clock cycle. While generating the partial designs, placement and mapping constraints are inserted into the design so that the design is placed column wise on the Virtex chip. The placement of the design is done so that it aids in the generation of partial bit-streams. In order to configure an individual pipeline stages, we developed a flow to generate partial bit-streams for pipeline stages. The flow uses guided place and route along with the JBits API to generate partial bit-streams. To control the flow of data, in and out of the pipeline stages, we presented a data flow controller that routes the data to and from the memory. And finally, to synchronize the reconfiguration and execution of the design, we presented a host controller to synchronize reconfiguration and execution of pipeline stages. To show the effectiveness of Virtual Pipelining, we executed our designs on the SLAAC-1V board. The results of our experiments indicated that there is a gain in throughput when a design is Virtually Pipelined when compared to the non-pipelined version. The gain in throughput is due to partial reconfiguration and pipelining. When the number of stages in the design is less than the number of stages that a device can fit, reconfiguration is not needed every clock cycle and hence the throughput gain is only due to increase in clock frequency because of pipelining.

Committee:

Dr. Ranga Vemuri (Advisor)

Keywords:

partial reconfiguration; virtex based board; virtual pipeline; JHDL; SBLOX (serial blocks)