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Lei, FeiranInjection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locke Loops (PLL-RIs)
Doctor of Philosophy, The Ohio State University, 2017, Electrical and Computer Engineering
Synchronization plays an important and fundamental role as the timing basis in digital, analog, and RF integrated circuits (ICs), where Phase-Locked Loops (PLLs) find their versatile applications. The noise sources in a traditional PLL are mainly divided into two groups: noise before the low-pass loop filter such as the noise in the reference signal, Frequency Divider (FD), Phase Frequency Detector/Charge Pump (PFD/CP); and noise after the filter such as the Voltage Controlled Oscillator (VCO) noise and the loop filter noise. The output phase noise of the PLL is the combined contribution from these two equally important in-band and out-band noise sources. This research studies the effect of the synchronization in the PLL on the decoupling of the 3dB bandwidths for different noise sources to achieve an optimum phase noise and improved locking behavior with an attenuated reference signal injection (RI) into a ring-type delay-line Voltage Controlled Synchronous Oscillator (VCSO). This dissertation begins with the development of a generalized phase model for both LC-type and ring-type VCSOs. Next, the relationship between the device baseband noise (flicker and thermal noise) and a ring-type oscillator's phase noise is derived. In addition, noise shaping functions are introduced to describe signal injection into the VCSO to achieve suppression of the oscillator in-band phase noise. Then, the transient and steady-state behavior of a Charge-Pump PLL-RI are explained with nonlinear differential equations and the phase-plane method. The nonlinear phase equation is linearized for the small-signal condition and the s-domain noise transfer functions as well as noise bandwidths are derived for different noise sources in the major components of the PLL-RI. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. The analysis is verified by the SPICE simulation and experimental results from a Charge-Pump PLL-RI using a 1GHz VCSO in GlobalFoundries 130nm standard CMOS technology. The designed VCSO occupies a core area of 0.005 mm$^2$, and operates from 0.5GHz to 1.7GHz. The PLL-RI, for first-harmonic locking applications, has a core area of 0.02 mm$^2$ and consumes 2.6mW power. When a 30dB attenuation is applied, phase noise at 1MHz and 10MHz offset are reduced from -118.8dBc/Hz (PLL) to -121.9dBc/Hz (PLL-RI), and -102.3dBc/Hz (PLL) to -128.3dBc/Hz (PLL-RI), respectively, with an integrated RMS jitter from 10KHz to 30MHz of 1.55ps. Finally, another application of the PLL-RI as an integer-N frequency synthesizer is studied and tested. The PLL-RI based frequency synthesizer with the ring-type VCSO achieves comparable noise performance with LC type PLLs, but uses a much smaller chip area and features lower power consumption. To summarize, this dissertation has throughly evaluated an oscillator and a PLL under small signal injection. Compared with the traditional PLL, the all-CMOS PLL-RI offers faster settling time, wider lock in range, and ability to decouple 3dB bandwidths for different noise sources to achieve an optimum noise performance. The applications of PLL-RIs can be extended to analog, digital, and RF systems for different timing schemes.

Committee:

Marvin White (Advisor); Waleed Khalil (Committee Member); Steven Bibyk (Committee Member)

Subjects:

Electrical Engineering

Keywords:

CMOS ICs; PLLs, Frequency Synthesizers, reference injection locking; phase noise suppression; jitter; low-frequency 1-f noise; thermal noise; RF measurements; device modeling parameter extraction; low power; adaptive tracking range; design and fabrication

Xu, HaoRuntime Leakage Control in Deep Sub-micron CMOS Technologies
PhD, University of Cincinnati, 2010, Engineering and Applied Science: Computer Science and Engineering

MOSFET scaling into deep sub-micro realm has resulted in significant increase in leakage power consumption. In 45nm technology generation and beyond, leakage power consumption will catch up with, and may even dominate, dynamic power consumption. This makes leakage power reduction an indispensable component for low power designs in deep sub-micro technologies. Many leakage control techniques have been introduced and studied so far. They can be characterized into two classes: runtime techniques and design-time techniques. Design-time techniques only modify the circuit and thus have limited capability of leakage reduction. On the other hand, runtime techniques tune the circuit into low-leakage mode according to the variation of circuit workload. When a circuit or a system has substantial slackness in its workload, runtime techniques can yield significant leakage saving. Hence runtime techniques, such as power gating and reverse body biasing, are widely used in industrial practices, and extensively studied in current researches as well.

Since the invention of runtime leakage control techniques (RTLC), most of they have been applied in a very crude manner. Several key questions regarding the design methodologies of RTLC remain unanswered, including how to design the optimum control policy, what is the optimum granularity of applying RTLC, and how to reduce leakage in circuit active mode. Before these questions are answered, RTLC can only be of an ad-hoc style. On top of these major questions, several other common problems in deep sub-micro technologies need to be considered before RTLC converges to a practical technique. These common problems include temperature and process variation, robustness issues in deep sub-micro technologies etc. They make the design of RTLC even more complicated and challenging.

In response to all these questions and challenges, our research aims at answering the major open questions of RTLC, tackling the practical problems in deep sub-micro technologies and finally forging a systematical solution for RTLC. To this end, this thesis studies the corresponding modeling, optimization, design methodology and design automation issues. Our whole study is driven by the following two main ideas. First, we consider that aggressive idleness exploitation is the key to achieve maximal leakage control. Second, we consider that applying RTLC in a finer manner is the key to enable aggressive idleness exploitation. Our study is based on two leakage control techniques: power gating and reserve body biasing. During our analysis, one type of RBB technique, Vth hopping, turns out to be more effective to control leakage in a finer manner. Therefore it becomes the center of our final solution.

Committee:

Ranganadha Vemuri, PhD (Committee Chair); Harold Carter, PhD (Committee Member); Chien-In Chen, PhD (Committee Member); Carla Purdy, C, PhD (Committee Member); Wen Ben Jone, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

CMOS digital design;Low power design;Leakage power control

WIGGERMANN, NEALCOMPLIANCE AND EVALUATION OF CODE FOR LOW ENERGY POWER OPERATED HANDICAP ACCESSIBLE DOORS
MS, University of Cincinnati, 2007, Engineering : Industrial Engineering
The Americans with Disabilities Act (ADA) of 1990 and the aging of the U.S. population has increased the attention given to the accessibility of public buildings to disabled individuals. Automated doors are a common method for providing access for the disabled, and their low energy operated counterparts offer a cost and possible energy savings over full automation. These doors, activated by the press of a button, are regulated by ADA code through an ANSI/BHMA standard. The purpose of this study was to measure the compliance of the doors as used in public, and to evaluate the standards that apply to these entryways. Doors were selected from different neighborhoods around the city of Cincinnati, Ohio from different categories of buildings (medical, education, government, recreation/arts, commercial/office, and retail/banking). Door opening times, location of the actuator, closing forces, and other physical attributes were recorded for each of 55 doors at 31 unique locations. Disabled door users experienced with one or more assistive devices were consulted to attempt to establish a link between door opening times and perceived difficulty of negotiating the doorway. 39% of the doors measured by the author were found to be noncompliant with ADA code in some way. The analysis suggests that there is no significant relationship between the perceived difficulty of the doorway and the time allowed for entry. The study recommends several simple and easy to implement changes to the ANSI/BHMA standard that can increase the safety and accessibility of many of these low energy power operated doors.

Committee:

Dr. Richard Shell (Advisor)

Keywords:

Handicap Accessible; Wheelchair; ADA Code; Low Power Energy Operated Door

Borowczak, MikeSide Channel Attack Resistance: Migrating Towards High Level Methods
PhD, University of Cincinnati, 2013, Engineering and Applied Science: Computer Science and Engineering
Our world is moving towards ubiquitous networked computing with unstoppable momentum. With technology available at our every finger tip, we expect to connect quickly, cheaply, and securely on the sleekest devices. While the past four decades of design automation research has focused on making integrated circuits smaller, cheaper and quicker the past decade has drawn more attention towards security. Though security within the scope of computing is a large domain, the focus of this work is on the elimination of computationally based power byproducts from high-level device models down to physical designs and implementations The scope of this dissertation is within the analysis, attack and protection of power based side channels. Research in the field concentrates on determining, masking and/or eliminating the sources of data dependent information leakage within designs. While a significant amount of research is allocated to reducing this leakage at low levels of abstraction, significantly less research effort has gone into higher levels of abstraction. This dissertation focuses on both ends of the design spectrum while motivating the future need for hierarchical side channel resistance metrics for hardware designs. Current low level solutions focus on creating perfectly balanced standard cells through various straight-forward logic styles. Each of these existing logic styles, while enhancing side channel resistance by reducing the channels' variance, come at significant design expense in terms of area footprint, power consumption, delay and even logic style structure. The first portion of this proposal introduces a universal cell based on a dual multiplexer, implemented using a pass-transistor logic which approaches and exceeds some standard cell cost benchmarks. The proposed cell and circuit level methods shows significant improvements in security metrics over existing cells and approaches standard CMOS cell and circuit performance by reducing area, power consumption and delay. While most low level works stop at the cell level, this work also investigates the impact of environmental factors on security. On the other end of the design spectrum, existing secure architecture and algorithm research attempts to mask side channels through random noise, variable timing, instruction reordering and other similar methods. These methods attempt to obfuscate the primary source of information with side channels. Unfortunately, in most cases, the techniques are still susceptible to attack - of those with promise, most are algorithm specific. This dissertation approaches high-level security by eliminating the relationship between high level side channel models and the side channels themselves. This work discusses two different solutions targeting architecture level protection. The first, deals with the protection of Finite State Machines, while the seconds deals with protection of a class of cryptographic algorithms using Feedback Shift Registers. This dissertation includes methods for reducing the power overhead of any FSM circuit (secured or not). The solutions proposed herein render potential side channel models moot by eliminating or reducing the model's data dependent variability. Designers unwilling to compromise on a doubling of area can include some sub-optimal security to their devices.

Committee:

Ranganadha Vemuri, Ph.D. (Committee Chair); Vijay Sundaresan, Ph.D. (Committee Member); Wen Ben Jone, Ph.D. (Committee Member); George Purdy, Ph.D. (Committee Member); Carla Purdy, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

Side Channel;Attack Resistance;High Level;FSM;Security;Low Power

Hu, XinRF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency and Controllable Bandwidth: Design Sythesis and Verification
Master of Science in Electrical Engineering (MSEE), Wright State University, 2017, Electrical Engineering
The double-balanced Gilbert mixer is widely used in RF receivers. In general, it is desirable to design a wide tuning frequency Gilbert mixer for low power, high conversion gain, low noise figure, and good linearity, but they are not easy to attain simultaneously. Therefore, trade-offs always exist by tuning design parameters. To observe the trade-off relationship between each tunable parameter and to make a mixer achieve specified requirements easily (i.e., tuning frequency range, bandwidth, and power), an automated design synthesis and verification approach for Gilbert mixer is proposed. A wide tuning CMOS Gilbert mixer design synthesis while keeping the local oscillator frequency of 2 GHz is presented as an example. Designed in 180 nanometer CMOS process, the tunable Gilbert mixer achieves a tuning frequency span of 2 GHz (1.1 - 3.1 GHz), a controllable bandwidth of ~50 MHz, a high conversion gain (0.5 – 6.4 dB), a low noise figure (6.81 – 8.36 dB), and a power of 9 mW.

Committee:

Henry Chen , Ph.D. (Advisor); Yan Zhuang, Ph.D. (Committee Member); Jiafeng Xie, Ph.D. (Committee Member)

Subjects:

Electrical Engineering; Engineering

Keywords:

Wide Tuning Frequency; Controllable Bandwidth; Low Power; High Conversion Gian; Low Noise Figure; Good Linearity; Trade-offs

Saidev, SriramDesign of a Digitally Enhanced, Low Power, High Gain, High Linearity CMOS Mixer and CppSim Evaluation
Master of Science, The Ohio State University, 2016, Electrical and Computer Engineering
The objective of this work is to develop a new technique of digitally controlled, second order linearization of an active mixer, along with incorporation of other standard linearization techniques. The performance of various techniques was studied and the one suitable for this design was chosen. The digital control stems from the fact that the second order non linearity is a result of the mismatch introduced in the switching pair. The system level design tool CppSim was also explored to conclude the ability to transfer the cadence design points to CppSim. Various simulations were done to check the performance of the mixer. The choice of bias points for optimal gain and linearity were explored

Committee:

Steven Bibyk (Advisor); Wladimiro Villarroel (Committee Member)

Subjects:

Electrical Engineering; Engineering

Keywords:

CppSim, Mixer, CMOS, High Gain, High Linearity, Low Power, Gilbert Cell, Digital IIP2, CCPD, IIP3 enhancement, IIP2 enhancement, 90nm,

Zhang, BinFPGA Design of a Multicore Neuromorphic Processing System
Master of Science (M.S.), University of Dayton, 2016, Electrical Engineering
Neuromorphic computing architecture has developed rapidly during recent years. Neuronmorphic network processor FPGA implementation is 3x and 127x faster than Intel E8400 processor with edge detection applications and ECG applications respectively. Considering resource utilization and system stability, a hardware-controlled communication routing network is a better choice than a time-delay based routing network. The separation of data lines prevents the hardware-controlled communication routing network from turning into a large network.

Committee:

Tarek Taha (Advisor); Keigo Hirakawa (Committee Member); Eric Balster (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Neuronmorphic Network; micro-processor; FPGA; ultra-low power processor

Jhaveri, Shaival GClock Frequency Drift with Power Droop in GPU Chips
MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering
GPU chips consume hundreds of watts of power when fully loaded as they undergo a large number of switching activities. This excessive switching activity can cause a sudden drop in power supply voltage, which is known as power droop. The main objective of this thesis is to understand the relationship between clock frequency and power droop. To establish the relationship we performed SPICE simulations and replicated the phenomenon of power droop to observe its effect on clock frequency. We define the observed effect of power droop to be Clock Frequency Drift Effect – wherein, the greater the power droop, the lower the frequency at which the clocks run. Industrial results are generated on a silicon GPU chip using Verigy 93K ATE and through LVx (Laser Voltage Extraction) control to strengthen the point of frequency degradation. On average, a frequency degradation of 18.33% was observed through the LVx results. We have also done a review on low capture power solutions to show how those solutions reduce toggle count which in turn mitigates the effect of power droop and thereby improves frequency.

Committee:

Carla Purdy, Ph.D. (Committee Chair); Bonita Bhaskaran, Ph.D. (Committee Member); Xuefu Zhou, Ph.D. (Committee Member)

Subjects:

Computer Engineering

Keywords:

GPU;LVx;Switching activity;Power Droop;Clock frequency;Low-power

SEKHAR, SANDHYAA DISTANCE BASED SLEEP SCHEDULE ALGORITHM FOR ENHANCED LIFETIME OF HETEROGENEOUS WIRELESS SENSOR NETWORKS
MS, University of Cincinnati, 2005, Engineering : Computer Engineering
This thesis describes the concept of sensor networks which has been made viable by the convergence of MEMS system technology and efficient routing protocols. Sensor nodes possess finite, non-renewable energy that they expend in sensing a multitude of modalities including temperature, moisture, pressure, light and infrared radiation. A radio-interconnected collection of such sensors forms a sensor network and the information collected from the network is transmitted for analysis at a distant location termed as the sink. The main purpose of a sensor network is to gather information about the various parameters of the area in which it is deployed and to transmit this information to the sink for appropriate utilization. A wireless sensor node is capable of only a limited amount of communication and processing. Therefore, unlike traditional networks, where the objective is to maximize channel throughput, the chief consideration in a sensor network is to extend the system lifetime as well as system robustness. Wireless ad hoc and sensor networks are comprised of energy–constrained nodes. This limitation has led to the dire need for energy-aware protocols to produce an efficient network. Heterogeneity is introduced in a wireless sensor network by having a large number of low power sensor nodes and a small number of more powerful nodes to serve as cluster heads. We propose a self-tuning scheme that improves the lifetime of a heterogeneous wireless sensor network by appropriately scheduling the transmission rate of individual sensor nodes in the network. We consider a distance based sleep scheduling problem for equal energy consumption rates in low power sensor nodes and evaluate the optimal settings required in a heterogeneous sensor network. We evaluate the efficiency of our proposed algorithm based on an analytical model and perform simulations to verify the adequacy of our scheme in terms of important network parameters and compare with existing heterogeneous sensor networks. We provide an estimate of the optimal number of clusters required, expected energy in a cluster head and the extent of network coverage. The proposed scheme is observed to improve network lifetime while conserving energy and maximizing information gathering at the sink.

Committee:

Dr. Dharma Agrawal (Advisor)

Subjects:

Computer Science

Keywords:

Energy-aware systems; Low-power design; Mobile environments; Heterogeneous Sensor networks; Wireless Sensor Networks

Ramesh, AnishaTUNNELING BASED QUANTUM FUNCTIONAL DEVICES AND CIRCUITS FOR LOW POWER VLSI DESIGN
Doctor of Philosophy, The Ohio State University, 2012, Electrical and Computer Engineering
Handheld devices, such as cellphones, dominate consumer electronics market today and are foreseen to grow further in future years. One of the primary challenges with these devices is reducing the power consumption while keeping the operating frequencies high. Scaling of transistor dimensions has contributed to both increasing chip operating frequencies and greater functionality per unit area. However, as dimensions enter a few 10’s of nanometer, leakage currents have also increased, escalating the overall power consumption. Scaling of supply voltage is a key to keep both dynamic and static power consumption low. Tunneling-based devices are investigated to address this challenge. Tunnel diodes in conjunction with conventional transistors can be used in novel circuit topologies to develop high speed circuits operating below 0.5V. However, large scale manufacture requires a Si-based device structure that can be fabricated with tools compatible with standard CMOS processing. In this dissertation, Si-based resonant interband tunnel diodes (RITD) are fabricated using chemical vapor deposition (CVD). High peak to valley current ratio's (PVCR) of 5.2 are obtained through optimization of the boron δ-doping with peak current densities of 20 A/cm2. This is the largest PVCR for silicon based tunnel diodes fabricated using CVD. Further, integration into a standard electronic design automation (EDA) tools is essential to enable development of very large scale integrated (VLSI) circuits. Tunnel diodes have been integrated into the Cadence EDA tool and a 32 x 32 bit tunneling SRAM (TSRAM) memory array has been designed with a standard 90 nm product development kit (PDK) obtained from MOSIS, for use as embedded memory. This provides a platform to compare TSRAM performance with the currently dominant SRAM and embedded DRAM technologies. Its performance and robustness to process variation is evaluated for a supply voltage of 0.5V. Read access times of 1 ns and write access times of 0.5 ns are obtained with a standby power dissipation of 6e-5 mW/cell and dynamic power dissipation of 1.8e-7 mW/MHz per cell. These are comparable to the 90 nm SRAM specifications obtained from the international technology roadmap for semiconductors (ITRS). Tunnel FETs are a promising alternate to MOSFETs for low power design due to the ability to scale threshold voltage and hence supply voltage, without increase in OFF currents. However, they suffer from low ON currents. Prior experience with tunnel diode optimization is used to investigate new TFET structures to improve tunneling ON currents. A 300 nm channel Si vertical p-TFET with an n δ-doping has an ON current of 0.05 µA/µm at a VDS of 2.5V with an ION-IOFF ratio of 104. Addition of Ge in the channel, to form a for a 30 nm Si0.9Ge0.1 channel, enhances the ON current to 4.8 µA/µm at a VDS of 2V.

Committee:

Paul Berger (Advisor); Marvin White (Committee Member); Patrick Roblin (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Resonant tunneling; TSRAM; Tunnel diodes; low power VLSI; Tunnel FET

Samsukha, ParasWireless Multichannel Recording/Stimulation System for Neurodynamic Studies of Aplysia
Doctor of Philosophy, Case Western Reserve University, 2009, EECS - Electrical Engineering

In this research, a bi-directional wireless implantable unit and an externaltransceiver which can be used for recording and stimulating neural activity of marine mollusk Aplysia Californica, has been developed. The system supports bidirectional wireless telemetry in a saltwater environment, using frequency shift keying (FSK) at 27.1 MHz to transmit data at 62.5 kbps data rate, and using on-off Keying (OOK) at 125 kHz to receive commands. The implanted device is powered using a 3-V, 160-mAh lithiumion battery, consumes 21 mW of power, weighs 21.9 gm including the battery, is 4.5 cm by 1.8 cm in size and can operate for 23 hr continuously before the battery dies. Measurement of acute neural activity from a live animal has been demonstrated using this device.

A fully monolithic bandpass amplifier for neural signal recording in large arrays has been designed and tested. The measured passband gain is 37.9 dB from 25 Hz to 15 kHz and input-referred noise is 1.04 μV rms, with a power consumption of 162 μW and a die area of 0.13 mm2 in a standard 0.5-μm CMOS process. The technology is also demonstrated via a 2x2-mm, fully integrated 4-channel application specific integrated circuit (ASIC) in 0.5-μm technology. The ASIC features a three-stage frontend amplifier which provides a maximum gain of 80 dB. The power consumption has been optimized considering the noise (1-μV r.m.s), bandwidth (2 kHz) and resolution (8-bits) requirements. The calculated power consumption per channel of the front end amplifier is 22 μWatt.

The architecture and the performance of the ASIC are scalable to multiple channels. As such, the device could serve as the basis for a closed-loop controller for prosthetic devices or deep brain stimulation.

Committee:

Steven Garverick, PhD (Advisor); Hillel Chiel, PhD (Committee Member); Massood Tabib-Azar, PhD (Committee Member); Pedram Mohseni, PhD (Other)

Subjects:

Biomedical Research; Electrical Engineering; Engineering

Keywords:

Neural recording; implantable; wireless; low power; multichannel

Pan, XiangDesigning Future Low-Power and Secure Processors with Non-Volatile Memory
Doctor of Philosophy, The Ohio State University, 2017, Computer Science and Engineering
Non-volatile memories such as Spin-Transfer Torque Random Access Memory (STT-RAM), Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), etc. are emerging as promising alternatives to DRAM and SRAM. These new memory technologies have many exciting characteristics such as non-volatility, high density, and near-zero leakage power. These features make them very good candidates for future processor designs in the power-hungry big data era. STT-RAM, a new generation of Magnetoresistive RAM, in particular is an attractive class of non-volatile memory because it has infinite write endurance, good compatibility with CMOS technology, fast read speed, and low read energy. With its good read performance and high endurance, it is feasible to replace SRAM structures on processor chips with STT-RAM. However, a significant drawback of STT-RAM is its higher write latency and energy compared to SRAM. This dissertation first presents several approaches to use STT-RAM for future low-power processor designs across two different computing environments (high voltage and low voltage). Overall our target is to take advantage of the benefits of STT-RAM over SRAM to save power and at the same time try the best to accommodate STT-RAM's write drawbacks with novel solutions. In high voltage computing environment, we present a low-power microprocessor framework -- NVSleep, that leverages STT-RAM to implement rapid checkpoint/wakeup of idle cores to save power. In low voltage computing environment, we propose an architecture - Respin, that consolidates the private caches of near-threshold cores into unified L1 instruction/data caches that use STT-RAM to save leakage power and improve performance. On top of this shared L1 cache design, we further propose a novel hardware virtualization core management mechanism to increase resource efficiency and save energy. Although the non-volatility feature of non-volatile memories can be leveraged to build power-efficient designs, it also brings in security concerns as data stored in these memories will be persistent even after system power-off. In order to address this potential security issue, this dissertation deeply studies the vulnerabilities of non-volatile memory as processor caches when exposed to "cold boot" attacks and then proposes an effective software-based countermeasure to eliminate this security threat with reasonable performance overhead.

Committee:

Radu Teodorescu (Advisor); Feng Qin (Committee Member); Christopher Stewart (Committee Member); Yinqian Zhang (Committee Member)

Subjects:

Computer Engineering; Computer Science

Keywords:

Non-Volatile Memory, STT-RAM, Low-Power Processor Architecture, Cache, Near-Threshold Computing, Process Variation, Security, Secure Processor Design, Cold Boot Attack

Qi, YangjieFPGA Based High Throughput Low Power Multi-core Neuromorphic Processor
Master of Science (M.S.), University of Dayton, 2015, Electrical Engineering
The interest in specialized neuromorphic computing architectures has been increasing recently, and several applications have been shown to be capable of being accelerated on such platforms. This thesis describes the implementation of multicore digital neuromorphic processing systems on FPGAs. Static and Dynamic routing were used to allow communication between the cores on the FPGA. Several applications were mapped to the system including image edge detection, MNIST image classification, and biometric ECG classification. Given that all the applications were implemented on the same processor (hence same base Verilog code), with only a change in the synaptic weights and number of neurons utilized, the system has the capability to accelerate a broad range of applications.

Committee:

Tarek Taha (Committee Chair); Vijayan Asari (Committee Member); Eric Balster (Committee Member)

Subjects:

Computer Engineering; Electrical Engineering

Keywords:

FPGA; Neural Network; Static Routing; Dynamic Routing; Low Power; High Throughput

Lien, E-JenEFFICIENT IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOGRAPHY IN RECONFIGURABLE HARDWARE
Master of Sciences (Engineering), Case Western Reserve University, 2012, EECS - Electrical Engineering
Elliptic curve cryptography (ECC) has emerged as a promising public-key cryptography approach for data protection. It is based on the algebraic structure of elliptic curves over finite fields. Although ECC provides high level of information security, it involves computationally intensive encryption/decryption process, which negatively affects its performance and energy-efficiency. Software implementation of ECC is often not amenable for resource-constrained embedded applications. Alternatively, hardware implementation of ECC has been investigated – in both application specific integrated circuit(ASIC) and field programmable gate array (FPGA) platforms – in order to achieve desired performance and energy efficiency. Hardware reconfigurable computing platforms such as FPGAs are particularly attractive platform for hardware acceleration of ECC for diverse applications, since they involve significantly less design cost and time than ASIC. In this work, we investigate efficient implementation of ECC in reconfigurable hardware platforms. In particular, we focus on implementing different ECC encryption algorithms in FPGA and a promising memory array based reconfigurable computing framework, referred to as MBC. MBC leverages the benefit of nanoscale memory, namely, high bandwidth, large density and small wire delay to drastically reduce the overhead of programmable interconnects. We evaluate the performance and energy efficiency of these platforms and compare those with a purely software implementation. We use the pseudo-random curve in the prime field and Koblitz curve in the binary field to do the ECC scalar multiplication operation. We perform functional validation with data that is recommended by NIST. Simulation results show that in general, MBC provides better energy efficiency than FPGA while FPGA provides better latency.

Committee:

Swarup Bhunia (Advisor); Christos Papachristou (Committee Member); Frank Merat (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Elliptic curve cryptography; ECC; MAHA; MBC; FPGA; low-power; encryption; security

Wang, FengEnergy Efficient Digital Baseband Modulator for Cable Terminal Systems Targeted on Field Programmable Gate Array
Master of Science (MS), Ohio University, 2004, Electrical Engineering & Computer Science (Engineering and Technology)

This thesis presents design and research in energy efficient digital baseband modulator for cable terminal systems targeted on field programmable gate array (FPGA). The design specifications of the individual processing blocks of digital baseband modulator are reviewed. Existing low power design techniques at algorithm and architecture levels are examined and their effectiveness for low power design on FPGA is investigated based on the power dissipation characteristics of the FPGA. Low power design strategy for the digital modulator is then derived. Finally, the implementation options for several key modules are investigated and the design space of power and area product is explored. In this design, a new parallel finite field multiplier is proposed, the interleaving algorithm is reformulated and rescheduling is used in the TCM modulator to achieve the low power goal. The results of this research show that most of the low power design techniques, except parallelizing, are very effective for energy efficient design in FPGA.

Committee:

Janusz Starzyk (Advisor)

Keywords:

Low Power; FPGA; Modulator

Sethuraman, BalasubramanianNovel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices
PhD, University of Cincinnati, 2007, Engineering : Computer Science and Engineering
International Technology Roadmap for Semiconductors (ITRS) project the latest trend moving towards a system-level and platform-based design, involving large percentage of design reuse. Different Intellectual Property (IP) cores, including processor and memory, are interconnected to build a typical System-on-Chip (SoC) architectures. Larger SoC designs dictate the data communication to happen over the global interconnects. At 45 nm and below, interconnects have profound impact on the performance (and power), due to increased delays and cross-coupling from multiple sources. Hence, attaining timing closure with reasonable performance and low power is increasingly becoming impractical. Also, the traditional bus based interconnection architectures present synchronization nightmare in a heterogenous System-on-Chip environment. At system level, the performance of the shared-bus start to deteriorate with increased number of cores. Networks-on-chip (NoC) has been proposed as a new design paradigm to solve the communication and performance bottlenecks in the modern System-on-Chip designs. Unlike the shared-bus approach, the central idea in an NoC is to implement interconnection of various IP cores using on-chip packet-switched networks. Due to reduced development costs and shorter design cycles and Time-To-Market, reconfigurable devices, especially, the FPGAs are increasingly being used in low/medium volume applications in place of their ASIC counterparts. Due to the scalability issues present in the use of shared-bus, NoC is gaining attention in the latest FPGA-based SoCs. In spite of the advantages, being a typical shared network, an NoC suffers from bottlenecks involving hop latency, congestion, bandwidth violations and increased area. In this thesis, we innovate and implement novelty to realize efficient Networks-on-Chip using commercial Xilinx FPGAs. We present tangible solutions for the issues that plague the efficient Networks-on-Chip implementation on the reconfigurable fabric. First, we concentrate this area overhead issue, the solutions to which actually resulted in many-fold advantages. Area is at a premium on an FPGA and therefore, the communication network should be as small as possible. The on-chip micro network area can be reduced by: (1) Using a simple router without sacrificing on the performance, and (2) Reducing the number of routers. Implementing the first idea, we develop a light weight parallel router (LiPaR), with multiple optimizations that resulted in a significant reduction logic area usage. The highlight of this dissertation remains in the translation of the second idea with the proposition of a novel router design that can handle multiple logic cores simultaneously, without any performance penalty. The new Multi Local Port Router (MLPR) provided many-fold advantages including reduction in area, power, transit time & congestion, and most importantly, bandwidth optimization, resulting in an efficient and high performance NoC design. Essentially, the MLPR is a marriage between switch-based and router-based interconnection network. A NoC system comprising MLPRs represents a complex design environment and hence, generation of an efficient Network-on-Chip configuration is a great challenge. We present an exhaustive-search based optiMap algorithm (finding optimal solutions) and a heuristic based fast mapping cMap algorithm. The results portray a dramatic reduction in the latency as well as the number of packets flowing in the NoC mesh. All the ports of an MLPR have the same mesh co-ordinate, thus, providing an opportunity to multicast to all the cores attached to the same MLPR, exploiting which we present a modified router architecture called Multi2 Router. Utilizing the multicast capability, we present an energy-efficient NoC configuration generation approach (uMap), targeting data packet traffic reduction in the network. Optimization for performance, latency or area constraints favor addition of more ports onto a single router. But, after extensive experimentation, we find a point of diminishing returns with regard to the power efficiency in using larger MLPRs. In addition to the average power increase, we observe the occurrences of several IR drop violations with increased port count, thus presenting a tradeoff between performance and power efficiency. Task graphs in modern SoCs are not static in nature and the variations in the intercommunication patterns and bandwidth requirements need to taken into consideration during NoC architecture generation. Hence, we present technique to estimate the Minimum BandWidth Guarantee (MBWG) required for a given topology and extend to find the NoC architecture minimizing the MBWG, thereby, helping prevent surprises in terms of bandwidth violations. In summary, the dissertation presents novel and efficient router designs, supported by the NoC architecture generation algorithms. Despite having an FPGA bias, the ideas proposed in this research are equally applicable to ASICs, thus, improving and taking forward an efficient NoC design flow.

Committee:

Dr. Ranga Vemuri (Advisor)

Keywords:

Networks-on-Chip (NoC); System-on-Chip (SoC); FPGA; Reconfigurable and Platform-Based Design; Light Weight Router Design; Multi Local Port Router; Multicast Router; Low Power Topology Generation and Mapping; Power Issues and IR drop Analysis

Li, KeFault Modeling and Detection for Gated-Ground SRAM
MS, University of Cincinnati, 2010, Engineering : Computer Engineering
In this research, a gated-Ground SRAM circuit has been implemented to study fault behaviors of single spot defects. All possible functional fault models of a single cell (FFM1s) and two adjacent cells (FFM2s) have been simulated under normal mode and sleep mode. Six new faults have been found. The new fault behaviors of a gated-Ground SRAM cell have been compared with those in a drowsy SRAM cell, and the commonality has been identified. Compared to traditional SRAM cells, both gated-Ground and drowsy SRAM cells are weak in data retention state, especially under sleep mode or drowsy mode if there exists any spot defect. A march test has been improved to cover both traditional static faults and gated-Ground faults, so that all single spot defects can be detected.

Committee:

Wen Ben Jone, PhD (Committee Chair); Ranganadha Vemuri, PhD (Committee Member); Carla Purdy, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

fault behaviors;fault detection;gated ground;low power SRAM;power gating

Han, QiangAn Error-Tolerant Dynamic Voltage Scaling Method for Low-Power Pipeline Circuit Design
MS, University of Cincinnati, 2012, Engineering and Applied Science: Computer Engineering
In recent years, many innovative researches have been conducted on dynamic voltage scaling (DVS), such as Razor [1]. This thesis presents an error-tolerant DVS design that can enhance the reliability and reduce the power consumption of a pipeline circuit simultaneously. Based on delay distributions of all pipeline stages, an efficient voltage island partitioning method is developed to cluster all pipeline stages into several voltage islands. By assigning the best voltages to stages, the DVS design can enable the pipeline stages to work at an optimal energy consumption with least performance penalty. Experimental results obtained by HSPICE and Matlab simulations demonstrate the feasibility of this method.

Committee:

Wen Ben Jone, PhD (Committee Chair); Carla Purdy, PhD (Committee Member); Ranganadha Vemuri, PhD (Committee Member)

Subjects:

Computer Engineering

Keywords:

VLSI;Low power design;Dynamic voltage scaling;Pipeline circuit;

Bakula, Casey J.LOW-POWER PULSE-SHAPING FILTER DESIGN USING HARDWARE-SPECIFIC POWER MODELING AND OPTIMIZATION
Master of Science, University of Akron, 2008, Electrical Engineering

This thesis presents a design process for decreasing the power consumption of pulse-shaping filters (PSF), whose purpose is to limit radio transmissions to a specified channel. A hardware layout is assumed based on a low-power application, and a power model of the assumed hardware is developed that approximates the number of logic-stage output transitions that occur in the adder that computes the PSF output. The number of transitions is used as a cost function in a simulated annealing optimization routine that perturbs the ideal PSF coefficients in an effort to find a lower-cost alternative to the ideal PSF. The parameters that dictate the convergence properties of the simulated annealing routine were carefully tailored to this application. It is shown that, given enough time, the optimization routine will find a PSF that closely resembles the ideal PSF, but with considerably lower power consumption.

Using a set of PSFs that would be typical for this application, savings between 18.4% and 74.5% of dynamic power consumption were achieved with insignificant distortion of the frequency response. It is observed that the amount of distortion can be controlled by changing the distance that the coefficients may be perturbed from their ideal values. The data presented here suggest that this distance can be very small and significant power savings can still be found, and a limit is suggested as to how large this distance can be before the distortion in the frequency response of the optimized PSF begins to outweigh the savings in power.

Committee:

Joan Carletta (Advisor)

Keywords:

pulse-shaping filter; low-power; power modeling; simulated annealing; adder modeling; coefficient perturbation

Zhang, DuoDYNAMIC CMOS MIMO CIRCUITS WITH FEEDBACK INVERTER LOOP AND PULL-DOWN BRIDGE
Master of Science in Engineering (MSEgr), Wright State University, 2013, Electrical Engineering
Two novel techniques, feedback inverter loop and pull-down bridge, adopted for multiple-input multiple-output (MIMO) dynamic CMOS circuits have been proposed in this thesis. The pull-down bridge technique optimizes the area and power of a single stage MIMO dynamic CMOS circuits, and the feedback inverter loop (FIL) technique improves the speed of multiple-stage dynamic CMOS circuits. Applying the pull-down bridge to the MIMO dynamic CMOS seven segment decoder, it is shown that common paths of different outputs are shared and optimized, which accounts for 12% speed improvement, 48% power reduction, and 73% area saving, as compared to the conventional logic design. Next, an optimized 64-bit binary comparator implemented by mixed-static-dynamic CMOS with FILs is presented. After partitioning the conventional dynamic CMOS into a mixed-static-dynamic CMOS, optimizing transistor sizes and using the FILs on the critical paths, the proposed design achieves 60% speed improvement and 42% power reduction, as compared to the conventional 64-bit dynamic CMOS comparator.

Committee:

Henry Chen, Ph.D. (Advisor); Marian K. Kazimierczuk, Ph.D. (Committee Member); Yan Zhuang, Ph.D. (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Multiple Input Multiple Output, dynamic CMOS, high-speed, low power

He, HaiboDynamically Self-reconfigurable Systems for Machine Intelligence
Doctor of Philosophy (PhD), Ohio University, 2006, Electrical Engineering & Computer Science (Engineering and Technology)

This dissertation is focused on the development of system level architectures and models of dynamically self-reconfigurable systems for machine intelligence. This research is significant for building brain-like intelligent systems. Although the development of deep submicron very large scale integration (VLSI) system, nanotechnology and bioinformatics facilitate building such intelligent systems, yet it is very challenging to study how these kinds of complex, reconfigurable systems can self-develop their connectivity structures, accumulate knowledge, make associations and predictions, dynamically interact with environment, and self-control to accomplish desired tasks.

A new framework of “learning-memory-prediction” for machine intelligence is proposed in this research, and it serves as the foundation for building intelligent systems through learning in dynamic value systems, memorizing in self-organizing networks, and predicting in hierarchical structures. These systems are characterized by on-line data driven learning, distributed structure of processing components with local and sparse interconnections, dynamic reconfigurability, self-organization, and active interaction with environment.

Learning is the fundamental element for biologically intelligent systems. The proposed online value system is able to learn and dynamically estimate the value of any multi-dimensional data set, and such value system can be used in reinforcement learning. Feedback mechanism is introduced in the self-organizing learning system to allow the machine to be able to memorize information in its distributed processing elements and make associations. After the information is learned and stored in the associative memory, a biologically-inspired anticipation-based temporal sequence learning architecture is proposed. All systems proposed in this research are hardware-oriented. A novel computing paradigm that can achieve low power consumption for designing large scale, high density intelligent systems is proposed, and a brief description of the system level hardware architecture for prototyping and testing of the proposed systems is also presented.

Intelligent systems have wide applications from military security systems to civilian daily life. In this research, different application problems, including pattern recognition, classification, image recovery, and sequence learning, are presented to show the capability of the proposed systems in learning, memory, and prediction.

Committee:

Janusz Starzyk (Advisor)

Keywords:

Reconfigurable systems; Machine intelligence; Learning, memory and prediction mechanism; Value system; Associative memory; Sequence learning; Low power design

Bontupalli, VenkatarameshIntrusion Detection and High-Speed Packet Classification Using Memristor Crossbars
Master of Science (M.S.), University of Dayton, 2015, Electrical Engineering
Intrusion Detection Systems (IDS) are intelligent specialized systems designed to interpret intrusion attempts from incoming network traffic. IDSs aim at minimizing the risk of accessing unauthorized data and potential vulnerabilities in critical systems by examining every packet entering a system. Packet inspection and Pattern matchings are often computationally intensive processes and that are the most power hungry functionalities in network intrusion detection systems. This thesis presents a high throughput, low latency and low power memristor crossbar architecture for packet header and payload matching that could be used for high-speed packet classification and malware detection. The memristor crossbar systems can perform intrusion detection through a brute force approach for static contents/signatures and a state machine approach for regular expressions. A large portion of the work completed in this thesis has been published in [1-2].

Committee:

Tarek Taha, Dr (Advisor); Eric Balster, Dr (Committee Member); Vamsy Chodavarapu, Dr (Committee Member)

Subjects:

Computer Engineering; Electrical Engineering

Keywords:

Intrusion Detection; Memristor Crossbars; High Speed Packet Classification; Low Power; Network Security; SNORT; String Matching; Regular Expression Matching

Wu, Pei-MingMicromachined On-Chip Fluxgate Magnetometers with Low Power Consumption
PhD, University of Cincinnati, 2010, Engineering : Electrical Engineering
A new micromachined on-chip magnetometer with low power consumption has been designed, fabricated, and fully characterized in this research work. Based on permalloy magnetic core, two novel CMOS-compatible micro fluxgate sensors have been developed and characterized in terms of low power consumption. In addition, a low-power interface integrated circuit has been developed and characterized for the developed sensors. Experiment shows that the magnetometer combined with the micro fluxgate sensor and the interface circuit consumes power comparable to that of the other state-of-the-art magnetometer systems. First, a micromachined ring-core fluxgate sensor utilizing localized core saturation method to reduce its power consumption is presented. The design is accomplished through 3D electromagnetic simulation. A low power design has achieved the power consumption of 14.4 mW and sensitivity of 590 V/T at 60 μT with an excitation current of 80 mA. Based on the design, fabricated devices have shown the power consumption of 14 mW and sensitivity of 650 V/T at 60 μT with an excitation current of 75 mA. The simulation and the experimental results showed a good agreement, which supports the new approach for the design of low-power fluxgates valid. In addition, measurements using a second harmonics-based detection circuit have been adopted, so the noise, stability and perming effect of the fabricated device are explored. Second, a new micro orthogonal fluxgate sensor with solenoid sensing coils is presented. The sensor consumes the power of 16 mW with an excitation current of 140 mA. The sensor occupies an active area of merely 2 mm by 0.15 mm with sensitivity of 0.1 V/T and linearity of 2.5 %. Its temperature coefficient of offset drift shows only 125 nT/°C even with such small sensitivity. This sensor type shows great potential to be manufactured with small size, low power, and high performance with low cost. Finally, a pulse-operating interface integrated circuit that can reduce the total power consumption of a fluxgate magnetometer is introduced and developed. The circuit works under power supply of +/-2.5V with 75 mA current driving capability. Total power consumption of 14 mW is achieved in the magnetometer comprised of the circuit and the first low power micro fluxgate sensor. The overall system sensitivity is 250 V/T. The corresponding rms noise is 400 nT/√Hz at 1 Hz. In this research work, a low power magnetometer system based on micro fluxgate sensors with permalloy magnetic core and pulse-operating integrated IC has been developed and successfully characterized. The newly developed sensors can have numerous applications that are previously untouched by the conventional fluxgate sensors that are bulky, expensive, and high power consumption

Committee:

Chong Ahn, PhD (Committee Chair); Marc Cahay, PhD (Committee Member); Joseph Nevin, PhD (Committee Member); Sang Young Son, PhD (Committee Member); Punit Boolchand, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Fluxgate;Low power;magnetic sensor;CMOS;MEMS

Han, SijingDesign and Modeling Environment for Nano-Electro-Mechanical Switch (NEMS) Digital Systems
Doctor of Philosophy, Case Western Reserve University, 2013, EECS - Computer Engineering
In this thesis, we study models for an innovative type of Nano-Electro-Mechanical Switch (NEMS) at the physical, logical and circuit level. NEMS are switching devices, which have virtually zero leakage current, 1-3 V operation voltage, 1-10 ns switching time, and small footprint. NEMS switches can be easily hybridized with CMOS at the metallization or device levels to manage leakage current and power. Our fabricated NEMS switches enable the implementation of a digital switching function using four times fewer switches than traditional approaches. In particular, the design of basic two-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT and BUF) can be implemented on a single NEMS switch. We design a compact and ultra-low power NEMS FPGA using these devices. The FPGA implementation uses a four-input CLB, which requires only eight NEMS switches and at most two mechanical delays per computation. In contrast, CMOS CLBs require over 150 traditional switches. By reducing the number of devices, our approach improves yield, reproducibility, speed, and power and simplifies the implementation. To accurately evaluate the performance of NEMS digital systems, we derive a SPICE circuit simulation model (Macromodel) that allows the evaluation of the NEMS based systems using fast circuit simulation techniques with the same accuracy of a slow multi-physics 3D Finite Element Analysis (FEA) model. The 3D FEA model is constructed to capture the multi-physics phenomena of the switches using the FEA simulation tool (COMSOL Multi-physics). The 3D FEA model is calibrated using the fabricated device measurements. This ensures that the 3D FEA physical device model produces the results that are similar to the results obtained from the fabricated device measurements. Using the 3D FEA physical model, we present a procedure to extract mechanical parameters which are used in developing the mechanical lumped model. The NEMS Macromodel is integrated into a circuit simulator enabling the evaluation of NEMS devices in an electrical design environment. The accuracy of the NEMS Macromodel is verified using the device properties derived from the 3D FEA models and measured from the fabricated devices. Using the circuit simulator, we measure the power dissipation of NEMS designs and compare them to the CMOS digital designs. Our experiment shows three to four times of magnitude improvement in power reduction for the NEMS technology over CMOS. This technology could be an alternative technology in implementing portable battery-power systems that are limited by the battery life and the ambient environments.

Committee:

Daniel Saab (Committee Chair); Marc Buchner (Committee Member); Francis Merat (Committee Member); Christos Papachristou (Committee Member); Massood Tabib-Azar (Committee Member)

Subjects:

Computer Engineering

Keywords:

NEMS; low power; digital circuit design; FPGA design; 3D FEA model; circuit simulation model

Guttman, JeremyPolymer-based Tunnel Diodes Fabricated using Ultra-thin, ALD Deposited, Interfacial Films
Master of Science, The Ohio State University, 2016, Electrical and Computer Engineering
Conjugated p-p bonded polymers offer a wide range of new electronic devices which have developed as a unique niche in the marketplace with an ever-growing need for integration. In particular, polymer-based tunnel diodes (PTDs) which exhibit negative differential resistance (NDR) at room temperature can be integrated with other novel components to realize memory and logic cells for highly manufacturable, roll-to-roll (R2R) printed electronics. The research presented here focuses primarily on the fabrication and operating principles behind PTDs. By incorporating an ultra-thin TiO2 interfacial tunneling barrier into a modified organic light emitting diode (OLED) structure, reproducible NDR can be realized. By varying the properties of the interfacial tunneling oxide, characteristics of NDR such as the peak-valley-current-ratio (PVCR), peak current density (J_peak), and the voltage at the peak density (V_peak) can be improved for memory and logic. This work successfully demonstrates room temperature NDR in PTDs using ultra-thin TiO2 interfacial tunneling barriers grown via atomic layer deposition (ALD). The intention of this work is to present a viable prototype PTD using ALD to deposit the tunneling barrier. By taking a look at the physical and electrical behavior behind the ALD deposited films, a better understanding can be gained on the nature of interfacial layer. It is suggested that localized defect states caused by oxygen vacancies induced during oxide growth is behind the tunneling behavior observed in the PTDs. By controlling the oxide growth, the crystal structure can be altered in order modify the oxygen vacancy concentration and therefore improve PVCR. Therefore, a key aspect of this thesis will be to observe how morphology, realized through varying temperature of ALD growth, can affect device characteristics. Additionally, to fully classify these devices, the physics behind the electrical operation needs to be further evaluated. Mapping the properties of the various materials through experimentation and modeling will serve as the starting place for future work to come. Finally, this thesis is part of an ongoing exploration for low-power, low-cost printed electronics. Therefore, a key aspect of this work is to present an argument for a printable process on a flexible, plastic substrate, and as such the requirement for a low temperature deposition is imperative. Low temperature ALD can come in the form of alternative precursors or alternative tunneling oxides. Moreover, by choosing to use alternative oxides, lower power NDR appearing at lower voltages may be realized. This study begins the work on finding alternative tunneling oxides that demonstrate similar oxygen vacancies observed in TiO2 films. In this case, Ta2O5 replaces TiO2 as the tunneling barrier. The initial data is promising, demonstrating a drop in the NDR voltage by approximately half compared to its TiO2 counterpart. Moreover, this work bolsters the claim that NDR is the result of a trap-based tunneling event through a defined defect band in the ALD deposited tunneling oxides. Though this thesis focuses solely on PTDs, the materials and processes demonstrated can be applied towards research interested in the conductivity properties of metal-oxides in addition to being useful for further work performed in the field of plastic electronics.

Committee:

Paul Berger (Advisor); George Valco (Committee Member)

Subjects:

Chemistry; Electrical Engineering; Engineering; Nanoscience; Nanotechnology; Organic Chemistry; Physical Chemistry; Physics; Plastics; Polymer Chemistry; Solid State Physics; Technology

Keywords:

polymer; organic; NDR; Negative Differential Resistance; Tunneling; IoT; Internet of Things; ALD; Atomic Layer Deposition; TiO2; Ta2O5; Memory; Logic; Low-power; flexible; printable; disposable; thin-film; oxygen vacancy; metal-oxide; defect; solid-state

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