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Imbulgoda Liyangahawatte, Gihan Janith MendisHardware Implementation and Applications of Deep Belief Networks
Master of Science in Engineering, University of Akron, 2016, Electrical Engineering
Deep learning is a subset of machine learning that contributes widely to the contemporary success of artificial intelligence. The essential idea of deep learning is to process complex data by abstracting hierarchical features via deep neural network structure. As one type of deep learning technique, deep belief network (DBN) has been widely used in various application fields. This thesis proposes an approximation based hardware realization of DBNs that requires low hardware complexity. This thesis also explores a set of novel applications of the DBN-based classifier that will benefit from a fast implementation of DBN. In my work, I have explored the application of DBN in the fields of automatic modulation classification method for cognitive radio, Doppler radar sensor for detection and classification of micro unmanned aerial systems, cyber security applications to detect false data injection (FDI) attacks and localize flooding attacks, and applications in social networking for prediction of link properties. The work in this thesis paves the way for further investigation and realization of deep learning techniques to address critical issues in various novel application fields.

Committee:

Jin Wei (Advisor); Arjuna Madanayaka (Committee Co-Chair); Subramaniya Hariharan (Committee Member)

Subjects:

Artificial Intelligence; Computer Engineering; Electrical Engineering; Engineering; Experiments; Information Technology

Keywords:

deep belief networks; multiplierless digital architecture; Xilinx FPGA implementations; low-complexity; applications of deep belief networks; spectral correlation function; modulation classification; drone detection; doppler radar; cyber security

Shao, QiliangFPGA Realization of Low Register Systolic Multipliers over GF(2^m)
Master of Science in Electrical Engineering (MSEE), Wright State University, 2016, Electrical Engineering
Finite field multiplication over GF(2^m) is a critical component for elliptic curve cryptography (ECC). National Institute of Standards and Technology (NIST) has recommended five polynomials (two trinomials and three pentanomials) for ECC implementation. Although there are a lot reports available on polynomial basis multipliers, efficient implementation of a design with flexible field-size is quite rare. There is another basis to represent the field called normal basis. Normal basis multiplication over GF(2^m) is widely used in various applications such as elliptic curve cryptography (ECC). As a special class of normal basis with low complexity, Gaussian normal basis (GNB) has received considerable attention recently. In this paper, we first propose a novel low-complexity hybrid-size systolic polynomial basis multiplier based on a proposed novel hybrid-size (for both pentanomial and trinomial) algorithm for efficient systolization of finite field multiplications. Next, we propose a novel decomposition algorithm to develop a digit-level (DL) low critical-path delay and low register-complexity systolic structure for GNB multiplication over GF(2^m). For the hybrid-size systolic polynomial multipliers, both the theoretical and field-programmable gate array (FPGA) implementation show that, our proposed architectures have lower register-complexity than the existing ones. The proposed hybrid-size multiplier can also be extended to other field-size and can be used as a third-party intellectual property (IP) core for various cryptosystems. At the same time, the proposed systolic Gaussian normal basis multipliers can achieve both low critical-path and low register-complexity through the theoretical and application-specific integrated circuit (ASIC) comparisons with the existing GNB multipliers.

Committee:

Jiafeng Xie, Ph.D. (Advisor); Yan Zhuang, Ph.D. (Committee Member); Zhiqiang Wu, Ph.D. (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Gaussian normal basis; finite field multiplication; systolic structure; irreducible polynomials; low complexity; digit-level; low critical-path delay

Host, Nicholas KRealization of a Low Cost Low Complexity Traveling Wave Antenna
Doctor of Philosophy, The Ohio State University, 2015, Electrical and Computer Engineering
For satellite communications, traditional phased array antennas could offer advantages over reflector antennas such as increased functionality, conformality, and no feed blockage. However, phased array systems are complex and expensive and, thus, not commonly used for satellites. Indeed, many applications (radar, electronic warfare, communications, etc.) would greatly benefit from less expensive phased array systems. Thus, much effort has been invested into addressing these challenges. This dissertation aims to greatly improve the feasibility of traditional phased arrays by eliminating the array backend (the main source of cost and complexity). Specifically, we introduce a traveling wave array (TWA) concept using a single feedline whose propagation constant can be controlled to enable scanning. This is done using a small mechanical movement (<100mil) to adjust the feedline propagation constant. In this manner, the phase delivered to each element can be altered, enabling scanning. Of importance, beam steering is achieved with only one feed and one small mechanical movement (for any size linear array) without using individual phase shifters. Four specific TWA implementations are presented: 1) parallel plate waveguide (PPW) array, 2) trapezoidal wedge coplanar stripline (TWCPS) array, 3) vertical PPW array, and 4) metal PPW array. Each of these three TWAs is comprised of a 20+ element linear array with stable realized gain and low side lobe level (SLL) across -25°≤θ≤25° scanning range. This dissertation describes the design procedure for each TWA, including element, feed, termination, and aperture excitation. Fabrication procedures and challenges are provided. Fabrication for these unique TWA geometries is found to be a key challenge for the concept. Prototype measurements are compared to simulations. The dissertation culminates in the metal PPW array which overcomes many of the challenges encountered by the previous designs. The array achieves stable realized gain over -25°≤θ≤25° with high efficiency even for a small array size. The array is constructed almost entirely of aluminum and is CNC-machined for low cost. Overall, the developed Ku-Band TWA constitutes a very low cost, low complexity alternative to traditional phased array antennas as it uses a single feed and one mechanical movement to achieve beam steering.

Committee:

John Volakis (Advisor); Chi-Chih Chen (Advisor); Christopher Baker (Committee Member)

Subjects:

Electrical Engineering; Electromagnetics; Engineering

Keywords:

Traveling Wave Array; TWA; Propagation Constant; Dielectric Loading; Dielectric Plunger; Phased Array; Series Fed Array; Beam Scanning; Low Cost; Low Complexity

Chen, PingxiuqiFPGA realization of low register systolic all one-polynomial multipliers over GF (2m) and their applications in trinomial multipliers
Master of Science in Electrical Engineering (MSEE), Wright State University, 2016, Electrical Engineering
All-one-polynomial (AOP)-based systolic multipliers over GF (2m) are usually not con-sidered for practical implementation of cryptosystems such as elliptic curve cryptography (ECC) due to security reasons. Besides that, systolic AOP multipliers usually su¿er from the problem of high register-complexity, especially in field-programmable gate array (FPGA) platforms where the register resources are not that abundant. In this thesis, however, we have shown that the AOP-based systolic multipliers can easily achieve low register-complexity implementations and the proposed architectures can be employed as computation cores to derive e¿cient implementations of systolic Montgomery multipli-ers based on trinomials, which are recommended by the National Institute of Standards and Technology (NIST) for cryptosystems. In this paper, first, we propose a novel data broadcasting scheme in which the register-complexity involved within existing AOP-based systolic multipliers is significantly reduced. We have found out that for practical usage, the modified AOP-based systolic structure can be packed as a standard computation core. Next, we propose a novel Montgomery multiplication algorithm that can fully em-ploy the proposed AOP-based computation core. The proposed Montgomery algorithm employs a novel pre-computed-modular (PCM) operation, and the systolic structures based on this algorithm fully inherit the advantages brought from the AOP-based core (low register-complexity, low critical-path delay, and low latency) except some marginal hardware overhead brought by a pre-computation unit. The proposed architectures are then implemented by Xilinx ISE 14.1 and it is shown that compared with the existing designs, the proposed designs achieve at least 70.0% and 47.6% less area-delay product (ADP) and power-delay product (PDP) than the best of competing designs, respectively.

Committee:

Jiafeng Xie, Ph.D. (Advisor); Henry Chen, Ph.D. (Committee Member); Zhiqiang Wu, Ph.D. (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Finite field multiplication, systolic structure, low complexity, Montgomery algorithm, irreducible trinomials

Ji, BoDesign of Efficient Resource Allocation Algorithms for Wireless Networks: High Throughput, Small Delay, and Low Complexity
Doctor of Philosophy, The Ohio State University, 2012, Electrical and Computer Engineering

Designing efficient resource allocation mechanisms is both a vital and challenging problem in wireless networks. In this thesis, we focus on developing resource allocation and control algorithms for wireless networks that are aimed towards jointly optimizing over three critical dimensions of network performance: throughput, delay, and complexity.

We first focus on multihop wireless networks under general interference constraints, and aim to designing efficient scheduling algorithms that jointly optimize the network performance over different dimensions among the aforementioned three dimensions. We develop frameworks that enable us to design throughput-optimal scheduling algorithms that can reduce delays and/or incur a lower complexity in the following sense: smaller amount of required information, simpler data structure, and lower communication overhead.

We then turn to a simpler setting of single-hop multi-channel systems. A practically important example of such multi-channel systems is the downlink of a single cell in 4G OFDM-based cellular networks (e.g., LTE and WiMax). Our goal is to design efficient scheduling algorithms that achieve provably high performance in terms of both throughput and delay, at a low computational complexity. To that end, we first develop new easy-to-verify sufficient conditions for rate-function delay optimality in the many-channel many-user asymptotic regime (i.e., maximizing the decay-rate of the probability that the largest packet waiting time in the system exceeds a certain fixed threshold, as system size becomes large), and for throughput optimality in non-asymptotic settings. These sufficient conditions have been designed such that an intelligent combination of algorithms that satisfy both of the sufficient conditions allows us to develop low-complexity hybrid algorithms that are both throughput-optimal and rate-function delay-optimal. Further, we propose simpler greedy policies that are throughput-optimal and rate-function near-optimal, at an even lower complexity.

Finally, we investigate the scheduling problem in multihop wireless networks with flow-level dynamics. We explore potential inefficiency and instability of the celebrated back-pressure algorithms in the presence of flow-level dynamics, and provide interesting examples that are useful for obtaining insights into developing a unified throughput-optimal solution.

Our results in this thesis shed light on how to design resource allocation and control algorithms that can simultaneously attain both high throughput and small delay in practical systems with low-complexity operations. On the other hand, our studies also reveal that when flow-level dynamics is taken into account, even optimizing a single metric of throughput becomes much more challenging, not to mention achieving high network performance over all the three dimensions.

Committee:

Ness Shroff (Advisor); Ness Shroff (Committee Chair); Atilla Eryilmaz (Committee Member); Can Koksal (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Scheduling; Wireless Networks; High Throughput; Small Delay; Low Complexity; Fluid Limits; Large-Deviations Theory