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Sundaresan, VijayArchitectural Synthesis Techniques for Design of Correct and Secure ICs
PhD, University of Cincinnati, 2008, Engineering : Computer Science and Engineering

Integrated Circuits (ICs) are widely used in all applications and industries like smart cards, cell phones, set-top boxes, automobiles, avionics, space exploration and bio-instrumentation, to name a few. Traditional IC design flows and architectural synthesis techniques have been developed primarily for area, power and performance optimization. In recent years, as we move into the nanometer semiconductor process era, the ability to integrate large and complex applications on a single semiconductor die coupled with the all pervasive nature of the technology and its impact on our daily lives, have brought into prominence two important IC optimization constraints: Security and Correctness.

In this thesis, we have developed novel architectural synthesis techniques at cell-level, circuit-level and algorithmic-level, in a hierarchical standard-cell-based IC design framework, to design correct and secure ICs. Formulation as a hierarchical framework allows efficient partitioning of the design problem into several clearly-defined design steps at various levels of abstractions, with a clear understanding of each design step and ability to incorporate the requirements of subsequent design steps. Furthermore, unlike naive security-centric IC design flows where security and IC implementation constraints (area, power and performance) are typically considered as orthogonal and often conflicting optimization goals, in this thesis, we developed a novel paradigm that could be used to simultaneously optimize security as well as IC implementation constraints (area and power), at various hierarchical levels of IC design. Together, these architectural synthesis techniques fit well in today's highly productive modular IC design flows, and thus efficiently design correct and secure ICs.

Committee:

Ranga Vemuri, PhD (Committee Chair); Jintai Ding, PhD (Committee Member); Karen Tomko, PhD (Committee Member); Harold Carter, PhD (Committee Member); Wen-Ben Jone, PhD (Committee Member)

Subjects:

Computer Science

Keywords:

Integrated Circuit Design; EDA; CAD for VLSI; Cryptographic Hardware Design; Secure Embedded Systems; Architectural Synthesis

Zimmerman, Mark D.In Vivo RF Powering for Advanced Biological Research
Master of Sciences (Engineering), Case Western Reserve University, 2008, Electrical Engineering
A miniature, implantable, remote RF powering system for a small, un-tethered laboratory animal inside a cage is proposed. The proposed implantable device exhibits dimensions 6 mm x 6 mm x 2 mm and a mass of 100 mg including bio-compatible silicone coating. The external system consists of a Class-E power amplifier driving a tuned 15 cm x 25 cm coil. The implant device includes integrated “capacitor-free” RF to DC and power control circuitry. The full system provides 2 V VDD at up to 1 mA to implant electronics with < 200 μV DC variation, < 1 mV total RMS noise, and < 25 mVpp 4 MHz ripple and a 3 V supply to CMOS switches over a 10 cm x 20 cm operating region with an implant tilt angle of up to 60°. Additionally, an intelligent power control system is proposed that would reduce external system power consumption and cage temperature increase.

Committee:

Darrin Young (Advisor); Frank Merat (Committee Member); Steven Garverick (Committee Member)

Subjects:

Electrical Engineering

Keywords:

RF powering; regulator; RF electronics; integrated circuit; analog; electronics; power control

Connor, Mark AnthonyDesign of Power-Scalable Gallium Nitride Class E Power Amplifiers
Master of Science (M.S.), University of Dayton, 2014, Electrical Engineering
The need for high power, highly efficient, multi-band and multi-mode radio frequency (RF) and microwave power amplifiers in the commercial and defense wireless industries continues to drive the research and development of gallium nitride (GaN) devices and their implementation in the receiver and transmitter lineups of modern microwave systems. Unlike silicon (Si) or gallium arsenide (GaAs), GaN is a direct wide bandgap semiconductor that permits usage in high voltage and therefore high power applications. Additionally, the increased saturation velocity of GaN allows for operation well into the super high frequency (SHF) portion of the RF spectrum. For the power amplifier designer, active devices utilizing GaN will exhibit power densities almost an order of magnitude greater than comparably sized GaAs devices and almost two orders of magnitude greater than Si devices. Not only does this mean an overall size reduction of an amplifier for a given output power, but it allows GaN to replace specialized components such as the traveling-wave tube (TWT) and other circuits once deemed impossible to realize using solid-state electronics. Designs utilizing GaN in amplifiers, switches, mixers, etc., are able to meet the continually shrinking size, increased power, stringent thermal, and cost requirements of a modern microwave system. There are two relatively straight forward methods used to investigate the intrinsic power scaling properties of a GaN high-electron-mobility transistor (HEMTs) configured as a common source amplifier. The first method involves sweeping the applied drain to source voltage bias and the second method involves scaling the physical size of the transistor. The prior method can be used to evaluate fixed sized transistors while the latter method requires an understanding of the obtainable power density for a given device technology prior to fabrication. Since the power density is also a function of the drain to source voltage bias, an initial iterative component of the design cycle may be required to fully characterize the device technology. If a scalable nonlinear device model is available to the designer, the harmonic balance simulator in most computer aided design (CAD) tools can be used to evaluate device parameters such as the maximum output power and power added efficiency (PAE) using large signal load pull simulations. The circuits presented in this thesis address two power amplifier design approaches commonly used in industry. The first approach utilizes commercially available bare die GaN transistors that can be wire-bonded to matching circuitry on a printed circuit board (PCB). This technique is known as hybrid packaging. The second approach utilizes a fully integrated design or monolithic microwave integrated circuit (MMIC) and the process design kit (PDK) used to design, simulate and layout the power amplifier circuitry before submission to a foundry for fabrication. In both cases, the nonlinear transistor models are used to investigate the power scalability of class E mode GaN power amplifiers and the techniques used to implement such circuits. The design, results, and challenges of each approach are discussed and future work is presented.

Committee:

Guru Subramanyam, Ph.D. (Committee Chair); Robert Penno, Ph.D. (Committee Member); Weisong Wang, Ph.D. (Committee Member)

Subjects:

Electrical Engineering

Keywords:

gallium nitride; GaN; HEMT; power amplifier; class E; transistor; switch; reconfigurable; MMIC; power scaling; impedance matching; load-pull; RF; microwave; integrated circuit

Nobles, Robert StrattonDevelopment of a distributed design system for integrated circuit design using VAX 11/750 and scaldsystem computers
Master of Science (MS), Ohio University, 1986, Electrical Engineering & Computer Science (Engineering and Technology)

Development of a distributed design system for integrated circuit design using VAX 11/750 and scaldsystem computers

Committee:

Harold Klock (Advisor)

Keywords:

Development; Distributed Design System; Integrated Circuit Design; VAX 11/750; Scaldsystem computers

Benedik, ChristopherModeling and Minimization of Integrated Circuit Packaging Parasitics at Radio Frequencies
Doctor of Philosophy (PhD), Wright State University, 2013, Engineering PhD
Many integrated circuits are connected to their packaging pins through bondwires. Due to the low cost of bondwires, there is interest in extending operating frequencies or negating their effects in order to keep the price of packaged integrated circuits as low as possible. Bondwires function as lumped circuits consisting of inductors, capacitors, and resistors which can be modeled based on wire geometry. Knowing this, models can be created which approximate the effects of bondwires. With the knowledge of these models, compensation techniques can be implemented which will match the bondwire impedance to the signal line impedance. The effects of these elements on circuit operation is apparent on both signal and power lines to devices. This dissertation is going to present 1. A bondwire model based on physical characteristics of interconnections including neighboring wires. The model is tested against data from fabricated test fixtures, and results compared to those produced by current software. 2. A compensation method for performance degradation caused by bondwires at radio frequencies. Test fixtures implementing these methods are fabricated and checked with results compared to predictions. 3. A method of component stacking which can be used to attach passive components directly to IC die. -Use of above method to improve power distribution network (PDN) performance. Theoretical results are compared to measured test fixture results. -Use of above method to improve performance of off device filters through Q-factor improvement. Improvement verified through test and analysis of a physical test fixture.

Committee:

Saiyu Ren, Ph.D. (Advisor); Raymond Siferd, Ph.D. (Committee Member); Marty Emmert, Ph.D. (Committee Member); Marian Kazimierczuk, Ph.D. (Committee Member); Ronald Coutu, Ph.D. (Committee Member)

Subjects:

Electrical Engineering; Engineering

Keywords:

integrated circuit packaging; bondwire; power distribution network; scattering parameters; transmission line; transmission parameters; passive circuit modeling; radio frequency circuit modeling; impedance measurement; power supply decoupling

Pelini, Nicholas MichaelNetlist Security Algorithm Acceleration Using OpenCL on FPGAs
Master of Science in Computer Engineering, University of Dayton, 2017, Electrical and Computer Engineering
Integrated circuits continue to grow in number of transistors and design complexity. Production of many of these components are also outsourced to facilities in a number of countries. Therefore, there is a need to ensure all parts within a system are reliable and free from modification. Verification tools must be able to assess circuits down to a gate level but also be scalable to assess complex designs. In response to this problem, an accelerated version of the Integrated Circuit Verification Software is proposed to determine if a manufacturer design is the same as a known, reference design by comparing the two netlists. Optimizations are made to the Python code, and an FPGA hardware accelerated version of the code is created using OpenCL. Results of the OpenCL implementation show an 18x to 24x speedup across various netlists. Additionally, a netlist previously too large for verification tools to run is able to be tested by the OpenCL algorithm.

Committee:

Eric Balster (Advisor); Frank Scarpino (Committee Member); John Weber (Committee Member)

Subjects:

Computer Engineering; Electrical Engineering

Keywords:

OpenCL; netlist; FPGA; DFF; verification; security; Python; gate; ctypes; fan in; fan out; flatten; hash; integrated circuit; acceleration; speedup

Yakopcic, ChrisMemristor Device Modeling and Circuit Design for Read Out Integrated Circuits, Memory Architectures, and Neuromorphic Systems
Doctor of Philosophy (Ph.D.), University of Dayton, 2014, Electrical Engineering
Significant interest has been placed on developing systems based on the memristor, which was physically recognized in 2008. The memristor is a nanoscale non-volatile device with a large varying resistance range. Voltage pulses can be applied to the memristor to change its resistance, and the last programed resistance remains until another voltage pulse is applied. The unique properties present in this device give it the potential to further the advancement of many electronic systems, such as read out integrated circuits (ROICs) for digital cameras, high-speed on-chip memory circuits, and neuromorphic circuits capable of parallel analog computation. This work first describes the different memristor modeling techniques that have been proposed, followed by a new memristor model that this capable of reproducing the I-V curves and switching characteristics of many physical memristor characterizations very accurately. Circuits are then designed using this model for the three applications previously mentioned (ROICs, memory arrays, and neuromorphic computation). It is demonstrated that a memristor based ROIC circuit can significantly reduce the area of a unit cell given that a very small memristor element is used to replace a large integrating capacitor. It is also shown that the memristor can be used to reduce the total area of on-chip microprocessor memory. Given the nonvolatile property of memristors, they can also be used to store information without consuming power to hold their memory state. Lastly, memristors can be used to implement neuromorphic circuits where parallel computations are performed in the analog domain. Just as chemical pulses alter synaptic weights in brain tissue, voltage pulses can be applied to memristors to alter their conductivity. This work is completed in SPICE, which handles many low level circuit details using a very detailed memristor model. Novel circuit designs for three different applications are not only presented in this work, they are also simulated with a level of accuracy not accounted for in the current literature

Committee:

Tarek Taha, Ph.D. (Advisor); Andrew Sarangan, Ph.D. (Committee Member); Guru Subramanyam, Ph.D. (Committee Member); Muhammad Usman, Ph.D. (Committee Member)

Subjects:

Electrical Engineering

Keywords:

memristor, SPICE, memory, neuromorphic, device model, ROIC, readout integrated circuit

Kavimandan, Mandar DilipIntegrated Inductors
Master of Science in Engineering (MSEgr), Wright State University, 2008, Electrical Engineering

Integrated inductors, also called spiral inductors, on-chip inductors, or planarinductors, are inseparable part in radio frequency integrated circuits (RFICs). Increasing growth in RFICs from the past few decades has forced study of these components in greater detail. Apart from IC inductors, there are several components mounted on a chip - namely capacitors, resistors, MOSFETs, diodes etc. It is extremely important to understand the electrical and magnetic behavior of all these components. Electrical behavior of these components is easy to understand. However, the real challenge lies in realizing and predicting the magnetic behavior of components, namely, inductors and capacitors. Capacitors have their own physical model developed for accurate modeling, but for inductors there are many factors to be considered. As the frequencies in RFICs are in the GHz range, factors such as self resonant frequency (SRF), quality factor (Q), self and mutual inductance are critical to design due to the very small size of inductor. Past research in this field has made it possible to predict magnetic behavior accurately by theoretical methods and/or electromagnetic simulators. Apart from these simulators, various equations have been derived for accurate calculation of inductance related to several geometries. Lumped physical models developed in the past help to model parasitic elements most accurately.

This thesis concentrates on a brief study of integrated inductors, their construction and modeling. Different electromagnetic simulators available in the market are reviewed. A MATLAB based spiral and pi network calculators have been developed. Spiral calculators help to compare different equations while a pi calculator solves for parasitic components depending on substrate material, dielectric layer thickness, and metal oxide thickness. The main aim of this research was to design a theoretical design procedure for designing inductor internal dimensions. It has been described briefly with the design example. The proposed method makes it easy to design internal dimension such as the inner diameter (d), width (w), spacing (s), height (h), and number of turns (N). The results obtained are closer to the desired ones.

Committee:

Marian Kazimierczuk, Ph.D (Advisor); Raymond Siferd, Ph.D (Committee Member); Ronald Riechers, Ph.D (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Integrated Inductors; Planar Inductors; Spiral Inductors; Spiral Calculator; PCB Inductors; Integrated Circuit Transformers

Roham, MasoudWireless Multichannel Microsystems for Time-Share Chemical and Electrical Neural Recording
Doctor of Philosophy, Case Western Reserve University, 2010, EECS - Electrical Engineering

This project has developed single-chip wireless microsystems fabricated using a 0.5-µm double-poly triple-metal n-well CMOS process that incorporate three powerful neuromonitoring techniques: fast-scan cyclic voltammetry (FSCV) for monitoring neurotransmitter concentrations, extracellular electrophysiology for single-unit recording, and time-share recordings of these two techniques for quasi-simultaneous measurements of chemical and electrical neural activity at a single brain site in vivo. These devices also support electrical stimulation for focal activation of neural circuits.

In particular, a 1.1-mW, 5-mm2, 4-channel integrated circuit has been developed that can be dynamically configured to perform neurochemical monitoring using 300-V/s FSCV and neuroelectrical recording using extracellular electrophysiology. The chip architecture uses a 76-µW, 3rd-order, continuous-time delta-sigma modulator per channel that achieves an rms input-referred noise of 56.7 pA (dc-5 kHz) and 3.5 µV (1.1-5 kHz) for chemical and electrical neuromonitoring, respectively. The chip architecture also incorporates monolithic circuitry for generating FSCV and biphasic constant-current stimulus waveforms. It has been externally interfaced with carbon-fiber microelectrodes implanted acutely in the caudate-putamen of an anesthetized rat, and enables chemically resolved monitoring of electrically evoked dopamine release and its postsynaptic bioelectrical response at the same recording site. The dopamine limit of detection corresponding to a signal-to-rms noise ratio of three is estimated to be 16.7 nM, which compares favorably with the amplitude of phasic dopamine transients that varies in the range of 40 nM-1 µM.

The chip has also been packaged on a miniature rigid-flex substrate to develop an implantable device for investigating brain-behavior relationships in an ambulatory rat. The device successfully captures the effect of high-dose amphetamine administration on electrically and non-electrically evoked dopamine neurotransmission in the brain, demonstrating that the technology developed throughout the course of this project can indeed be applied to conduct neurochemical measurements in the context of behavior.

Committee:

Pedram Mohseni, PhD (Committee Chair); Dominique Durand, PhD (Committee Member); Steven Garverick, PhD (Committee Member); Paul Garris, PhD (Committee Member)

Subjects:

Biomedical Research; Electrical Engineering; Engineering

Keywords:

Amperometry; delta-sigma modulator; dopamine; fast-scan cyclic voltammetry; neurochemical monitoring; neuroelectrical recording; time-share neuromonitoring; wireless integrated circuit

Bakhshiani, MehranA SELF-SUSTAINED MINIATURIZED MICROFLUIDIC-CMOS PLATFORM FOR BROADBAND DIELECTRIC SPECTROSCOPY
Doctor of Philosophy, Case Western Reserve University, 2015, EECS - Electrical Engineering
This project has developed two integrated microsystems fabricated in a 0.35-µm two-poly four-metal RF CMOS process for miniaturized broadband dielectric spectroscopy. In particular, first, a broadband sensor interface IC as part of a miniaturized measurement platform for MHz-to-GHz dielectric spectroscopy has been developed. The IC measures frequency-dependent S21 magnitude and phase of a microfluidic dielectric sensor fabricated in a thick gold-on-glass microfabrication process and loaded with a material-under-test (MUT). The sensor interfaced with the IC is fully capable of differentiating among deionized (DI) water, phosphate buffered saline (PBS), ethanol and methanol in tests conducted at four different excitation frequencies of 50 MHz, 500 MHz, 1 GHz and 3 GHz. Further, dielectric readings of ethanol from the sensor interfaced with the IC at five excitation frequencies in the range of 50 MHz to 2 GHz are in excellent agreement (error < 1%) with those from using a vector network analyzer (VNA) as the sensor readout. Next, a self-sustained, miniaturized, microfluidic-CMOS platform for palmtop dielectric spectroscopy has been developed. The platform incorporates a parallel-plate capacitive sensor with a three-dimensional gap, floating electrode, and microfluidic channel for sample delivery, as well as a fully integrated transceiver for broadband dielectric spectroscopy. The IC applies a single-tone sinusoidal RF excitation signal in a frequency range of ~ 9MHz to 2.433GHz to the MUT-loaded sensor, and measures the sensor transmission characteristics in the voltage domain via an amplitude/phase measurement utilizing broadband frequency response analysis (bFRA) to extract the MUT complex permittivity with microliter sample volumes. Complex dielectric readings of PBS from the platform at six excitation frequencies in the range of 50 MHz to 2.4 GHz are in excellent agreement (RMS error <1.5% for 0.5 to 2.4 GHz) with those from a reference measurement by an Agilent 85070E dielectric probe kit interfaced with a VNA. Finally, an autonomous self-sustained palmtop platform, incorporating the microfluidic-CMOS platform, ADC, power supply unit, Wi-Fi module, and a Raspberry Pi computing module has been developed. The palmtop platform is capable of accurately measuring the real and imaginary parts of MUT complex permittivity from ~ 9MHz to 2.433GHz in less than 5s, enabling rapid, high-throughput, and low-cost measurements with a self-sustained, portable platform that can pave the way for translating dielectric spectroscopy from the lab bench to the field or the bedside.

Committee:

Pedram Mohseni (Advisor); Francis L. Merat (Committee Member); Soumyajit Mandal (Committee Member); Umut A. Gurkan (Committee Member); Michael A. Suster (Committee Member)

Subjects:

Engineering

Keywords:

Integrated Circuit, Broadband Dielectric Spectroscopy, Sensor, Microfluidic, CMOS, Miniaturized, Transceiver

Laha, SoumyasantaAnalysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs
Doctor of Philosophy (PhD), Ohio University, 2015, Electrical Engineering & Computer Science (Engineering and Technology)
Today's nanochips contain billions of transistors on a single die that integrates whole electronic systems as opposed to sub-system parts. Together with ever higher frequency performances resulting from transistor scaling and material improvements, it thus become possible to include on the same silicon chip analog functionalities and wireless communication circuitry that was once reserved to only an elite class of compound III-V semiconductors. It appears that the last stretch of Moore's scaling down to 5 nm range, these systems will only become more capable and faster, due to novel types of transistor geometries and functionalities as well as better integration of passive elements, antennas and novel isolation approaches. Accordingly, this dissertation is an example to how RF-CMOS integration may benefit from the use of a novel multi-gate transistors called FinFETs or Double Gate Metal Oxide Semiconductor Field Effect Transistors (DGMOSFETs). More specifically, this research is to validate how the performance of the radio frequency wireless communication integrated circuits can be improved by the use of this novel transistor architecture. To this end, in this dissertation, a wide range of radio frequency integrated circuits have been investigated in DG-MOSFETs which include Oscillators, On Off Keying (OOK) Modulator, Power Amplifier, Low Noise Amplifier, Envelope Detector, RF Mixer and Charge Pump Phase Frequency Detector. In all cases, the use of DG-MOSFET devices lead to reduction of transistor count and circuit complexity, while also resulting in tunable circuits owing to local back-gate control available in this device structure. Hence this work provides a unique insight as to how modest geometry changes and 3D device engineering may result in significant gains in analog/RF circuit engineering in the last stretch of Moore's scaling.

Committee:

Savas Kaya (Advisor)

Subjects:

Electrical Engineering

Keywords:

Radio Frequency Integrated Circuit Design; Wireless Communication; Double Gate MOSFET; 60 GHz; OOK Modulation and Demodulation; Oscillator; Power Amplifier; Low Noise Amplifier; RF Mixer; Phase Frequency Detector; 65 nm RF CMOS TRx Design

Gunawardena, SanjeevFeasibility study for the implementation of global positioning system block processing techniques in field programmable gate arrays
Master of Science (MS), Ohio University, 2000, Electrical Engineering & Computer Science (Engineering and Technology)

The Global Positioning System represents the pinnacle of navigation technology for the 21st century. As new technologies integrate GPS services, the limited availability of GPS in environments where the signal is severely attenuated, subject to strong multipath or high dynamics becomes an obstacle to a rapidly growing industry. A novel scheme for processing the GPS signal, namely a software radio employing block-processing techniques similar to those used for image processing has proven to enhance the usability of GPS in such environments. However, these techniques have huge computational requirements that are impossible to meet with a microprocessor. Custom designed hardware, such as an application specific integrated circuit (ASIC) would handle the processing requirement, but defeats the philosophy of a software radio since the algorithms cannot be changed. Field programmable gate arrays (FPGAs) are beginning to replace ASICs in certain applications since they feature software-like re-programmability while approaching ASIC-like performance. FPGAs are excellent candidates for research since they lack the NRE costs associated with ASICs. Hence, FPGAs are the most attractive implementation platform for developing a real-time block-processing GPS receiver.

This work lays the groundwork for the implementation of a real-time block-processing GPS receiver in FPGA hardware. It is a feasibility study since the problem is approached at a high-level of abstraction. The original block-processing approach is re-analyzed for implementation in FPGA hardware. Implementing the 5000-point FFTs in finite-precision hardware represents one of the biggest challenges in this work. This requires analysis of the FFT error bound to determine the minimum precision required that would yield acceptable results while minimizing hardware cost. Even though the analytical error bound for finite-precision FFTs is well documented in past literature, its direct application to the block-processing problem becomes too complex. This work employs statistical results of simulations to deduce the optimum hardware architecture and concludes that real-time capability can be achieved with currently available technology.

Committee:

Janusz Starzyk (Advisor)

Keywords:

Global Positioning System; GPS; block-processing technique; application specific integrated circuit; ASIC; FFT; Field programmable gate arrays; FPGA

Cong, PengWIRELESS BATTERYLESS IN VIVO BLOOD PRESSURE SENSING MICROSYSTEM FOR SMALL LABORATORY ANIMAL REAL-TIME MONITORING
Doctor of Philosophy, Case Western Reserve University, 2008, EECS - Electrical Engineering
Genetically engineered small laboratory animals with in vivo real-time physiological signals monitoring are ultimately crucial for system biology research to identify genetic variation susceptibility to various diseases and to develop effective treatment methods for similar human diseases. Blood pressure is one of the most important vital signals used in such research. However, there is no adequate solution for its chronic blood pressure monitoring to date. By merging MEMS technology and low power CMOS integrated circuits design through a high level system integration together with a conventional molding-based packaging technique, miniature, light-weight, wireless, batteryless, less-invasive, and implantable blood pressure sensing microsystems have been demonstrated for untethered small laboratory animals real-time monitoring. These critical features of the microsystem greatly suppress stress and post-implant trauma-induced information distortion. The proposed microsystem employs a miniature instrumented elastic sensing cuff, wrapped around a blood vessel, for blood pressure monitoring. The blood pressure is coupled into the sensing cuff caused by the vessel expansion and contraction. The microsystem can detect the pressure signal and wirelessly transmit the information to a nearby receiver with an adaptive RF powering capability to ensure a stable system power supply. The sensing technique avoids vessel penetration and substantially minimizes vessel restriction due to the soft cuff elasticity, thus attractive for long-term implant. A MEMS capacitive pressure sensor is designed and fabricated for its low temperature dependence, time stability, and zero DC power consumption. The integrated electronics consisting of a low power low-noise correlated-double-sampling capacitance-to-voltage converter, an 11-bit cyclic ADC, an adaptive RF powering system, an oscillator-based transmitter, and digital control circuitry have been designed and fabricated in a 1.5µm CMOS process. The prototype system achieves a 10-bit system resolution with 300µW power consumption. The ASIC and the MEMS sensor are interfaced with a 5mm-diameter RF powering coil over a thin flexible substrate and packaged with the blood pressure sensing cuff. The microsystems designed for laboratory rats and mice monitoring exhibit a weight of 430mg and 130mg, respectively. Untethered laboratory animals implant study demonstrates the microsystem capability of capturing real-time high-fidelity blood pressure information under a wireless and batteryless condition. Other bio-sensing channels such as core body temperature and EKG can be integrated into the prototype system architecture.

Committee:

Darrin Young, PhD (Advisor); Wen Ko, PhD (Committee Member); Dominique Durand, PhD (Committee Member); Steven Garverick, PhD (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Microsystem; Mixed-signal Integrated circuit design; Low power Low noise circuit; Medical device; implantable device; RF powering; wireless data telemetry

Bowman, David C.Image Stitching and Matching Tool in the Automated Iterative Reverse Engineer (AIRE) Integrated Circuit Analysis Suite
Master of Science in Computer Engineering (MSCE), Wright State University, 2018, Computer Engineering
Due to current market forces, leading-edge semiconductor fabrication plants have moved outside of the US. While this is not a problem at first glance, when it comes to security-sensitive applications, over-production, device cloning, or design alteration becomes a possibility. Since these vulnerabilities exist during the fabrication phase, a Reverse Engineering (RE) step must be introduced to help ensure secure device operation. This thesis proposes several unique methods and a collection of tools to ensure trust assurance in integrated circuit design by detecting fabrication flaws and possible hardware Trojans using several image processing techniques; fused into a singular view of the design. This suite of tools, the Automated Iterative Reverse Engineer (AIRE), addresses these security concerns. AIRE is comprised of an Image Stitcher, Stitch Assembler, Design Parser, Image Matcher, and IC Image Fusion Viewer. These tools work in concert to assist the design validation test engineers in assessing and analyzing the structure and performance of the IC. The first tool, the Image Stitcher, is the focus of this thesis.

Committee:

Marty Emmert, Ph.D. (Advisor); Travis Doom, Ph.D. (Committee Member); John Gallagher, Ph.D. (Committee Member)

Subjects:

Computer Engineering; Electrical Engineering

Keywords:

image processing; image stitching; image matching; reverse engineering; multimodal matching; hardware Trojans; hardware Trojan detection; integrated circuit

Majerus, Steve JWireless, Implantable Microsystem for Chronic Bladder Pressure Monitoring
Doctor of Philosophy, Case Western Reserve University, 2014, EECS - Electrical Engineering
This work describes the design and testing of a wireless implantable bladder pressure sensor suitable for chronic implantation in humans. The sensor was designed to fulfill the unmet need for a chronic bladder pressure sensing device in urological fields such as urodynamics for diagnosis and neuromodulation for bladder control. Neuromodulation would particularly benefit from a wireless bladder pressure sensor providing real-time pressure feedback to an implanted stimulator, resulting in greater bladder capacity while using less power. The pressure sensing system consists of an implantable microsystem, an external RF receiver, and a wireless battery charger. The implant is small enough to be cystoscopically implanted within the bladder wall, where it is securely held and shielded from the urine stream, protecting both the device and the patient. The implantable microsystem consists of a custom application-specific integrated circuit (ASIC), pressure transducer, rechargeable battery, and wireless telemetry and recharging antennas. Because the battery capacity is extremely limited, the ASIC was designed using an ultra-low-power methodology in which power is dynamically allocated to instrumentation and telemetry circuits by a power management unit. A low-power regulator and clock oscillator set the minimum current draw at 7.5 µA and instrumentation circuitry is operated at low duty cycles to transmit 100-Hz pressure samples while consuming 74 µA. An adaptive transmission activity detector determines the minimum telemetry rate to limit broadcast of unimportant samples. Measured results indicated that the power management circuits produced an average system current of 16 µA while reducing the number of transmitted samples by more than 95% with typical bladder pressure signals. The wireless telemetry range of the system was measured to be 35 cm with a bit-error-rate of 10-3, and the battery was wirelessly recharged at distances up to 20 cm. A novel biocompatible packaging method consisting of a silicone-nylon mesh membrane and a compliant silicone gel was developed to protect the sensor from water ingress while only reducing the sensor sensitivity by 5%. Dynamic offset removal circuitry extended the system dynamic range to 2,900 cm H2O but limited the sensor AC accuracy to 3.7 cm H2O over a frequency range of 0.002 – 50 Hz. The DC accuracy of the sensor was measured to be approximately 2.6 cm H2O (0.9% full-scale). Functionality of wired prototypes was confirmed in feline and canine animal models, and wireless prototypes were implanted in a female calf large-animal model. Measured in vivo pressure recordings of bladder contractions correlated well with reference catheters (r =0.893–0.994).

Committee:

Steven Garverick (Advisor); Swarup Bhunia (Committee Co-Chair); Margot Damaser (Committee Member); Pedram Mohseni (Committee Member); Christian Zorman (Committee Member)

Subjects:

Biomedical Engineering; Electrical Engineering

Keywords:

Implantable electronics; bladder pressure sensor; low-power; integrated circuit; wireless; chronic implantation; bladder implant; pressure sensor; power management; adaptive transmission rate; wireless battery recharge

Chadha, VishalDesign and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays
MS, University of Cincinnati, 2005, Engineering : Computer Engineering
One limitation of current FPGAs is that the user is limited to strictly digital electronic designs and are not suitable for multi-technology applications. In 2002, the novel idea of a Multi-technology Field Programmable Gate Array was proposed to extend the flexibility and reusability benefits of conventional FPGAs into multi-technology domain. But the chip design done for that work was not well suited for implementations in modern systems and was not compatible with modern CAD resources. Further, digital logic clusters did not include a dedicated carry-chain for arithmetic operations as in many FPGAs. In this thesis, research has been done to make the Multi-Technology Logic Cluster design much faster, smaller and versatile by using improved process technology, floorplanning and data processing capabilities so that these components match the performance expected from current applications. Hence, this is the next step in evolution of MT-FPGAs to provide high-performance solutions for complex applications.

Committee:

Dr. Fred Beyette Jr. (Advisor)

Keywords:

ASIC; Application specific integrated circuit; CMOS; Complementary Metal Oxide Semiconductor. Technology used to manufacture silicon; integrated circuits; Delay flip-flop or D-flop; The input is copied to the output delayed by one clock cycle; FPGA