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Zheng, YuLow-cost and Robust Countermeasures against Counterfeit Integrated Circuits
Doctor of Philosophy, Case Western Reserve University, 2015, EECS - Computer Engineering
Counterfeit integrated circuits (ICs) in a supply chain have emerged as a major threat to the semiconductor industry with serious potential consequences, such as reliability degradation of an end product and revenue/reputation loss of the original manufacturer. Counterfeit ICs come in various forms, including aged chips resold in the market, remarked/defective dies, and cloned unauthorized copies. In many cases, these ICs would have minor functional, structural and parametric deviations from genuine ones, which make them extremely difficult to isolate through conventional testing approaches. On the other hand, existing design approaches that aim at facilitating identification of counterfeit chips often incur unacceptable design and test cost. In this thesis, we present novel low-overhead and robust solutions for addressing various forms of counterfeiting attacks in ICs. The solutions presented here fall into two classes: (1) test methods to isolate counterfeit chips, in particular cloned or recycled ones; and (2) design methods to authenticate each IC instance with unique signature from each chip. The first set of solutions is based on constructing robust fingerprint of genuine chips through parametric analysis after mitigating the process variations. The second set of solutions is based on novel low-cost physical unclonable functions (PUFs) to create unique and random signature from a chip for reliable identification of counterfeit instances. We propose two test methods with complementary capabilities. The first one primarily targets cloned ICs by constructing the fingerprint from scan path delays. It uses the scan chain, a prevalent design-for-testability (DFT) structure, to create a robust authentication signature. A practical method based on clock phase sweep is proposed to measure small delay of scan paths with high resolution. The second one targets isolation of aged chips under large inter- and intra-die process variations without the need of any golden chips. It is based on comparing dynamic current fingerprints from two adjacent and self-similar modules (e.g., different parts of an adder) which experience differential aging. We propose two delay-based PUFs built in the scan chain which convert scan path delays into robust authentication signature without affecting testability. Another novel PUF structure is realized in embedded SRAM array, an integral component in modern processors and system-on-chips (SoCs), with virtually no design modification. It leverages on voltage-dependent memory access failures (during write) to produce large volume of high-quality challenge-response pairs. Since many modern ICs integrate SRAM array of varying size with isolated power grid, the proposed PUF can be easily retrofitted into these chips. Finally, we extend our work to authenticate counterfeit printed circuit boards (PCBs) based on extraction of boundary-scan path delay signatures from each PCB. The proposed approach exploits the standard boundary scan architecture based on IEEE 1149.1 standard to create unique signature for each PCB. The design and test approaches are validated through extensive simulations and hardware measurements, whenever possible. These approaches can be effectively integrated to provide nearly comprehensive protection against various forms of counterfeiting attacks in ICs and PCBs.

Committee:

Swarup Bhunia (Committee Chair); Christos Papachristou (Committee Member); Frank Merat (Committee Member); Philip Feng (Committee Member); Christian Zorman (Committee Member)

Subjects:

Computer Engineering

Keywords:

Counterfeit Integrated Circuits; Chip Fingerprint; Physical Unclonable Function; Golden-free Detection; Design for Test

Silwal, RoshanAsynchronous Physical Unclonable Function using FPGA-based Self-Timed Ring Oscillator
Master of Science in Electrical Engineering, University of Toledo, 2013, College of Engineering
Field Programmable Gate Array (FPGA) security has emerged as a challenging security paradigm in system design. Systems implemented on FPGAs require secure operations and communication. There is a growing concern over the security attributes of FPGAs regarding protecting and securing information processed within them, protecting designs during distribution and protecting intellectual property rights. One of the important aspects of improving the trustworthiness level of FPGAs is enhancing the physical security of FPGAs. A Physical Unclonable Function (PUF) provides a means to enhance physical security of Integrated Circuits (ICs) against piracy and unauthorized access. PUFs exploit the inherent and embedded randomness that occurs during the fabrication process of silicon devices. This thesis presents a novel FPGA-based PUF design technique using asynchronous logic. Significant process variations exist in IC fabrication, which makes each IC unique in its delay characteristics. The statistical delay variation in transistors and wires across FPGA chips is exploited through identically laid-out asynchronous ring oscillators. The asynchronous ring oscillators generate oscillations of varying frequencies when the oscillators are identically mapped on a semiconductor device. These varying frequencies produced by identically mapped self-timed ring oscillators are used to generate unique PUF response bits, which are used in device authentication and cryptographic applications such as generating secret keys and True Random Number Generator (TRNG). Experimental analysis shows that asynchronous oscillators of PUFs generate oscillations of varying frequencies, and the uniqueness for the PUF responses is 49.92%, which is very close to the desired 50% factor.

Committee:

Mohammed Niamat (Committee Chair); Robert C Green, II (Committee Member); Weiqing Sun (Committee Member)

Subjects:

Computer Engineering; Electrical Engineering

Keywords:

FPGA; STRO-PUF; Physical Unclonable Function; PUF; Self-Timed Ring Oscillator; Hardware Cryptography; Asynchronous Logic; Asynchronous Ring Oscillator

Choudhury, MuhtadiDesign and Analysis of a Novel Area-Efficient and Stage Configurable ROPUF
Master of Science, University of Toledo, Electrical Engineering
According to the Electronic Resellers Association International (ERAI), counterfeit incidents have been increasing progressively since 2008. Reconfigurable hardware like Field Programmable Gate Array (FPGA), as well as ASIC semiconductors, are prone to security vulnerabilities due to their increased outsourcing and widespread implementations; both being extensively used in covert military and competitive commercial applications. Hence, hardware tampering threats and design piracy pose a significant threat on FPGAs because of their far-reaching employments. Ring Oscillator Physical Unclonable Function (ROPUF) has demonstrated potential in solving substantial safety concerns due to its capacity to generate random, yet chip-unique keys, capitalizing on the process variation while withstanding cloning and external attacks. Process manufacturing variation is uncontrollable and even with the uniformity of the chip manufacturing process, manufacturing variations exist. The ROPUF structure, although promising for FPGA-based platforms, is not area efficient in terms of response bit per RO circuit implementation. In this research work, a four input Stage-Configurable ROPUF (SCROPUF) based on XOR gates and a functional block which significantly increases the output frequency comparison pairs are designed. Subsequently, implementation of the area efficient SCROPUF design and quality factors evaluation in terms of uniqueness, bit aliasing, uniformity parameters and the NIST Statistical Tests for Randomness is performed on six Xilinx Artix-7 FPGAs. The purpose of the extensible SCROPUF design, along with the functional logic block incorporated in the model is to ensure dynamic operation with all of the 16 input combinations. This makes the transformation from one through five stages feasible in a single design. The proposed design also introduces significant dynamic attributes in terms of varying average frequencies with change in the input configurations of the PUF model. With the novel selectivity features, a designer can choose the most suitable configuration for specific applications. Apart from generating high challenge and response pairs (CRPs) compared to the other designs, experimental analysis with SCROPUF shows that it has a high average static intra-chip variation to the dynamic component ratio suggesting high uniqueness and good reliability (reproducibility) due to low bit-flip probability. The Random Patch Mixer (RPM) technique implemented in this work to offset the systematic variation effect in the response bit-stream is corroborated by the successful NIST statistical tests, therefore making the design suitable for cryptographic and authentication purposes.

Committee:

Mohammed Niamat (Committee Chair); Mansoor Alam (Committee Member); Weiqing Sun (Committee Member)

Subjects:

Electrical Engineering

Keywords:

Physical Unclonable Function