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Experiments with Hardware-based Transactional Memory in Parallel Simulation
Hay, Joshua A

2014, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
Transactional memory is a concurrency control mechanism that dynamically determines when threads may safely execute critical sections of code. It does so by tracking memory accesses performed within a transactional region, or critical section, and detecting when memory operations conflict with other threads.
Transactional memory provides the performance of fine-grained locking mechanisms with the simplicity
of coarse-grained locking mechanisms.

Parallel Discrete Event Simulation is a problem space that has been studied for many years, but still
suffers from significant lock contention on SMP platforms. The pending event set is a crucial element to
PDES, and its management is critical to simulation performance. This is especially true for optimistically
synchronized PDES, such as those implementing the Time Warp protocol. Rather than prevent causality
errors, events are aggressively scheduled and executed until a causality error is detected.

This thesis explores the use of transactional memory as an alternative to conventional synchronization
mechanisms for managing the pending event set in a time warp synchronized parallel simulator. In particular, this thesis examines the use of Intel’s hardware transactional memory, TSX, to manage shared access to the pending event set by the simulation threads. In conjunction with transactional memory, other solutions to contention are explored such as the use of multiple queues to hold the pending event set and the dynamic binding of threads to these multiple queues. For each configuration a comparison between conventional locking mechanisms and transactional memory access is performed to evaluate each within the WARPED parallel simulation kernel. In this testing, evaluation of both forms of transactional memory (HLE and RTM) implemented in the Haswell architecture were performed. The results show that RTM generally outperforms conventional locking mechanisms and that HLE provides consistently better performance than conventional locking mechanisms, up to as much as 27%.
Philip Wilsey, Ph.D. (Committee Chair)
Fred Beyette, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
74 p.

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Hay, J. (2014). Experiments with Hardware-based Transactional Memory in Parallel Simulation. (Electronic Thesis or Dissertation). Retrieved from https://etd.ohiolink.edu/

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Hay, Joshua. "Experiments with Hardware-based Transactional Memory in Parallel Simulation." Electronic Thesis or Dissertation. University of Cincinnati, 2014. OhioLINK Electronic Theses and Dissertations Center. 18 Dec 2017.

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Hay, Joshua "Experiments with Hardware-based Transactional Memory in Parallel Simulation." Electronic Thesis or Dissertation. University of Cincinnati, 2014. https://etd.ohiolink.edu/

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