With the continued growth of mobile communications, large portions of the RF spectrum are being utilized for a variety of wireless applications. For next-generation
systems to adapt to this crowded and fluctuating wireless environment, future radio hardware must be capable of flexible and reconfigurable operation. Key to this endeavor is the development of high-performance digital-to-analog converters which can directly synthesize RF signals, bypassing the need for analog up-conversion and other RF processing by pushing functionality into the digital domain.
In this work, a multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is developed for direct digital-to-RF synthesis. The proposed architecture uses only a single clock frequency (fS) for RF generation and includes a reconfigurable ΔΣ modulator (DSM) that operates in band-pass (BP) and high-pass (HP) modes to synthesize signals around fS=4, fS=2, or 3fs=4. Analog interleaving via two 3-bit DACs is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM, increasing the SNR, and easing filtering requirements.
After a theoretical discussion, the proposed architecture is demonstrated by an initial prototype implemented in a 130 nm SiGe BiCMOS process and operating at fS = 2GHz. The design realizes a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50MHz bandwidth, and an in-band SFDR of 58.5 dB. In a second revision, an on-chip 14-bit DSM is included, implemented as an array of pipelined 1-bit pipelined subtracters to generate 3-bit, fS-rate input data. The second prototype also utilizes on-chip amplitude and timing calibration along with a CML data path to improve DAC speed, linearity, and SNR. Measurements at fS = 2GHz yield a 76.2 dB SIRR, 76.2 dB SFDR over a 100MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR and -66.4 dBc LTE ACLR.
To enable the high-speed data input required by the RF-DAC, a fully integrated, AC coupled pulse receiver is designed in support of this work. The low power and area efficient receiver is implemented as a fully integrated pulse receiver, eliminating the need for large, board-mounted capacitors. Additionally, the pulse receiver topology minimizes baseline wander with return-to-zero (RZ) signaling and removes the need for data encoding by internally latching long strings of continuous data. A common mode feedback circuit employs replica biasing to ensure operation over PVT variations and across various modes of operation. In a low and high power mode, the proposed receiver is tested up to 7.5 Gb/s and 10 Gb/s, respectively, achieving a peak operation effciency of 0.54mW/Gb/s and a BER < 10^-13.
Altogether, this work describes and validates a novel method of direct digital-to-RF synthesis. The design is traced from conceptual analysis through implementation and testing. Other circuits, such as the LVDS pulse receiver, are designed in support of this work and serve as an indicator of both the design challenges and opportunities found at the interface between the digital and RF domains.