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TEST PATTERN GENERATION FOR CROSSTALK FAULT IN DYNAMIC PLA
LIU, JIANXUN
2003, MS, University of Cincinnati, Engineering : Computer Engineering.
Crosstalk noise is one of the major noise problems introduced by interconnect wire scaling and high clock speeds. In modern DSM circuits, Signal crosstalk can arise between two long parallel wires. The programmable logic array (PLA) has been used in modern high speed circuit design because of its predictable delay. The PLA may suffer crosstalk noise problem which arises between long and parallel product lines. It is important and necessary to identify and test those crosstalk faults. In this research, we closely observed the crosstalk effect in dynamic PLAs. Based on the characteristics of the crosstalk, we used a hierarchical approach to generate test patterns for the crosstalk fault of each product line. Final test patterns are then compressed by test pattern compressor. At last a large set of MCNC benchmark circuit is experimented to show the efficiency of the ATPG algorithm.
Wen-Ben Jone (Advisor)
91 p.

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LIU, J. (2003). TEST PATTERN GENERATION FOR CROSSTALK FAULT IN DYNAMIC PLA. (Electronic Thesis or Dissertation). Retrieved from https://etd.ohiolink.edu/

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LIU, JIANXUN. "TEST PATTERN GENERATION FOR CROSSTALK FAULT IN DYNAMIC PLA." Electronic Thesis or Dissertation. University of Cincinnati, 2003. OhioLINK Electronic Theses and Dissertations Center. 20 Jun 2018.

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LIU, JIANXUN "TEST PATTERN GENERATION FOR CROSSTALK FAULT IN DYNAMIC PLA." Electronic Thesis or Dissertation. University of Cincinnati, 2003. https://etd.ohiolink.edu/

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