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An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University
Lee, Hoon-Kyeu

1986, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).

An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University

Janusz Starzyk (Advisor)
166 p.

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Lee, H. (1986). An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University. (Electronic Thesis or Dissertation). Retrieved from https://etd.ohiolink.edu/

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Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Electronic Thesis or Dissertation. Ohio University, 1986. OhioLINK Electronic Theses and Dissertations Center. 30 Jul 2015.

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Lee, Hoon-Kyeu "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Electronic Thesis or Dissertation. Ohio University, 1986. https://etd.ohiolink.edu/

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