Master of Science, University of Akron, 2017, Electrical Engineering

Radio frequency (RF) antenna array beamforming based on electronically steerable wideband phased-array apertures find applications in communications, radar, imaging and radio astronomy. High-bandwidth requirements for wideband RF applications necessitate hundreds of MHz or GHz frame-rates for the digital array processor. Systolic array architectures are often employed in multi-dimensional (MD) signal processing for linear and rectangular antenna arrays. Thus, this research used a FPGA hardware platform, the ROACH-2, which is equipped with a Xilinx Virtex-6 SX475T FPGA chip, and which is widely used in the field of radio astronomy. The research concentrated on the prospects of implementation of systolic array based MD beamformers on the ROACH-2, and on methods of extending the operating frequency to GHz range by using polyphase structures. The proposed systolic array architectures employ a differential form 2-D IIR frequency planar beam filter structure which is low in hardware utilization. The study highlights techniques that can be used to overcome the limitations of the ROACH-2 signal processing platform to achieve high operating frequencies.

Committee: Arjuna Madanayake (Advisor); Subramaniya Hariharan (Committee Member); Joan Carletta (Committee Member) Subjects: Communication; Electrical Engineering; Engineering

MS, University of Cincinnati, 2006, Engineering : Computer Engineering

Efficiently computing the Jacobi symbol (a/b) for integers a and b is an important step in a number of cryptographic processes. This thesis presents various algorithms for computing the Jacobi symbol and hardware implementations of two such algorithms. Both the algorithms are systolic and thus each can be implemented as an array of identical cells. The first algorithm for unsigned numbers is slower but also easier to implement in hardware than the second algorithm for signed numbers. The systolic nature of the algorithm is responsible for the space and time efficiency of the implementation. The simple and regular architecture lends itself very well to VLSI implementation and also makes it scalable. We wrote a VHDL description of both the algorithms. The description was used to obtain semi custom layout estimates and to implement the algorithms on Altera devices. Both the algorithms were also tested through simulation and on Altera devices.

Committee: Dr. Carla Purdy (Advisor) Subjects: