MS, University of Cincinnati, 2020, Engineering and Applied Science: Computer Engineering
In the face of the increasing cost of manufacturing semiconductor devices, many designers of Integrated Circuits (IC) have been electing to outsource the fabrication of ICs to pure play foundries in order to reduce manufacturing costs. However, this may lead to IC designs being stolen, counterfeited, maliciously modified, or otherwise mishandled by bad actors in the supply chain. In response, researchers have devised methods of thwarting such attacks against intellectual property in the IC supply chain. One such method is known as logic encryption.
Logic encryption is a hardware security strategy that adds key inputs, which require the correct secret key input, known only to the designer, to be applied for the circuit to have correct output behavior. The field of logic encryption has evolved over the past decade during which increasingly strong attacks and increasingly strong encryption strategies have been developed. However, the cost in terms of power, performance, and area (PPA) of implementing logic encryption has often been ignored in favor of increasing the level of security for proposed methods, and how well they protect against known attacks. Considering these costs is an important hurdle in transitioning the technology to commercial-grade designs, and a strategy for constraining the cost of logic encryption is needed.
A methodology for applying known logic encryption methods to a design is proposed in this work. In this methodology, named Constraint-Directed Logic Encryption (CDLE), potential encrypted versions of an IC design are considered. A designer can set the security requirement for encryption as well as power, performance, and area constraints, based on the design specification. There is a subset of designs that meet the security requirement and another that are within the PPA constraints. CDLE targets the overlap of these subsets, and maximizes security within it to produce an optimally encrypted design that meets the security requirement (open full item for complete abstract)
Committee: Ranganadha Vemuri Ph.D. (Committee Chair); John Emmert Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member)
Subjects: Computer Engineering