Doctor of Philosophy, The Ohio State University, 2019, Computer Science and Engineering

Machine learning is becoming an integral part of everyday life. Therefore, development of a high performance genre of machine learning algorithms is becoming increasingly significant from the perspectives of performance, efficiency, and optimization. The current solution is to use machine learning frameworks such as TensorFlow, PyTorch and CNTK, which enable us to utilize specialized architectures such as multi-core CPUs, GPUs, TPUs and FPGAs. However, many machine learning frameworks facilitate high productivity, but are not designed for high performance. There is a significant gap in the performance achievable by these frameworks and the peak compute capability of the current architectures. In order for machine learning algorithms to be accelerated for large-scale data, it is essential to develop architecture-aware machine learning algorithms. Since many machine learning algorithms are very computationally demanding, parallelization has garnered considerable interest. In order to achieve high performance, data locality optimization is extremely critical, since the cost of data movement from memory is significantly higher than the cost of performing arithmetic/logic operations on current processors. However, the design and implementation of new algorithms in machine learning has been largely driven by a focus on computational complexity. In this dissertation, the parallelization of three extensively used machine learning algorithms, Latent Dirichlet Allocation (LDA), Non-negative Matrix Factorization (NMF), and Word2Vec, is addressed by a focus on minimizing the data movement overhead through the memory hierarchy, using techniques such as 2D-tiling and rearrangement of data computation. While developing each parallel algorithm, a systematic analysis of data access patterns and data movements of the algorithm is performed and suitable algorithmic adaptations and parallelization strategies are developed for both multi-core CPU and GPU platforms. Experimental resul (open full item for complete abstract)

Doctor of Philosophy (Ph.D.), University of Dayton, 2016, Electrical Engineering

This thesis examined several acceleration efforts of knowledge mining from Cognitive Domain Ontologies (CDOs), which is a knowledge repository in the Cognitively Enhanced Complex Event Processing (CECEP) architecture. The CECEP architecture was developed at US Air force research laboratory. This is an autonomous decision support tool that reasons and learns like a human and enables enhanced agent-based decision-making. This architecture has applications in both military and civilian domains. Real time agents require massively linked knowledge databases to be searched using a large set of constraints to generate intelligent decisions in run time. One of the most computationally challenging aspects of CECEP is mining the domain knowledge captured in CDOs. The CDO mining process employed in the CECEP architecture is cast as a constraint-satisfaction problem (CSP). It falls into the category of NP-complete problems, which are very likely to require massive computing to solve. Even a small instance of an NP-complete problem in some cases could take years of computing to solve. Typically searching is a ubiquitous procedure to solve CSP problems, but sometimes constraint consistency is good enough to find a valid solution without performing a search. This thesis explored several CSP algorithms and deployed two different algorithms on heterogeneous hardware platform in order to mine CDOs. We initially examined the Exhaustive depth first search (EDFS) algorithm on a cluster of GPGPUs and Intel Xeon Phi co-processors. We achieved around 100 times speedup on a GPGPU compare to single CPU. Since the search space grows exponentially with the EDFS algorithm, this study explored an intelligent search algorithm that can prune the search space according to the constraints. We modified the conventional Forward Checking (FC) algorithm and introduced a novel path-based forward checking algorithm to mine CDOs and compared with a commonly utilized CSP solver. Conventional singl (open full item for complete abstract)

PHD, Kent State University, 2006, College of Arts and Sciences / Department of Computer Science

Over the years a number of variations on associative computing have been explored. At Kent State University (KSU), associative SIMD computing has its roots at Goodyear Aerospace Corporation, but most recently has focused on exploring the power of the associative computing paradigm as compared to traditional SIMD, and even MIMD, computing. In contrast, Prof. Robert Walker's research group at KSU has focused on implementing those associative concepts on a single chip by developing a new associative SIMD RISC processor, called the ASC (ASsociative Computing) Processor, using modern FPGA implementation techniques. This dissertation describes the development of a working, scalable, ASC Processor that is pipelined to improve performance, supports a reconfigurable network, can be specialized further for dedicated applications (e.g., genome processing), and that can realize the multiple SIMD (MSIMD) paradigm by supporting multiple control units. As a first step in this processor development, a Control Unit and a 4-PE Array developed previously by Master's students were integrated into the first working ASC Processor. This processor was then modified to develop the first scalable PE ASC Processor, and demonstrated on database processing and image processing. However, the core of this dissertation research was the design and implementation of a pipelined scalable ASC Processor, which as far as we are aware is the first working single-chip pipelined SIMD associative processor and perhaps the first single-chip pipelined SIMD processor in general. Compared to the first scalable ASC Processor, this pipelined processor not only gains the advantage of pipelining, but has a faster clock frequency due to a more efficient implementation. With that pipelined scalable ASC Processor as a base, two major architectural variations were explored. To support an innovative LCS algorithm for genome sequence comparison, the reconfigurable PE interconnection was modified with some features inspir (open full item for complete abstract)

MS, University of Cincinnati, 2012, Engineering and Applied Science: Computer Engineering

Parallel Discrete Event Simulation (PDES) is an active area of research for many years. Studies with PDES have focused primarily on either shared memory or distributed memory platforms. However, the emergence of low-cost multi-core and many-core processors suitable for use in Beowulf clusters provides an opportunity for PDES execution on a platform containing both shared memory and distributed memory parallelism. This thesis explores the migration of an existing PDES simulation kernel called WARPED to a Beowulf Cluster of many-core processors. More precisely, WARPED is an optimistically synchronized PDES simulation kernel that implements the Time Warp paradigm. It was originally designed for efficient execution on single-core Beowulf Clusters. The work of this thesis extends the WARPED kernel to contain parallel threaded execution on each node as well as parallelism between the nodes of the cluster. The new version of warped will be called threaded WARPED. In this thesis, warped is redesigned with thread safe data structure protected by various constructs. In particular atomic instructions are used to deploy lock-free data-structures and synchronization. With the addition of thread to WARPED the work also required adjustments and extensions to several of the subalgorithms of Time Warp. In particular, adjustments to the algorithm for computing Global Virtual Time (GVT), and termination detection were required. This thesis explains the modifications made to implement threaded WARPED and evaluates the performance capabilities of the two solutions for managing the shared data structures.

MS, Kent State University, 0, College of Arts and Sciences / Department of Computer Science

Basic tasks for Air Traffic Control will be implemented using NVIDIA's CUDA language on a NVIDIA device and compared to the performance of an Associative SIMD processor doing the same tasks. To do this, we create a simulation of an airfield with constantly moving aircrafts. The tasks that will be used in the evaluation are: tracking and correlation, collision detection, and collision resolution. These are the most compute intensive of the Air Traffic Control tasks, so they will give us a good measure of the capabilities of the NVIDIA device. The first task is tracking and correlation of the aircrafts in a 256 nautical mile by 256 nautical mile bounding area on a 2D plane with varying altitudes. This task is executed once each half second during each 8 second major cycle period and uses radar to correlate the exact location of the aircraft and its flight records. During every 8 second cycle, Batcher's algorithm is used to check if any aircraft's projected path has a possibility for collision. If a potential collision is possible within the next 20 minutes, we first locate a collision free path for one of them and then have it switch to this path. In previous research, the ability of a multicore system to perform basic ATC tasks was investigated. The graph showing its performance increased rapidly as the number of aircraft increased, which is consistent with the general belief that all large real-time systems require exponential time. In contrast, in our earlier research, an associative SIMD system was shown to be able to execute these basic tasks in linear time with a graph that had a very small slope. Additionally, the multicore regularly missed a large number of deadlines while the SIMD system did not miss a single deadline. Our goal here was to determine whether we could get SIMD-like results using a CUDA implementation of the same real-time system involving basic ATC tasks on a NVIDIA accelerator. Our research shows that our NVIDIA accelerators can provide a SIM (open full item for complete abstract)

Master of Science (MS), Wright State University, 2015, Computer Science

Visualization is an important task in data analytics, as it allows researchers to view abstract patterns within the data instead of reading through extensive raw data. Allowing the ability to interact with the visualizations is an essential aspect since it provides the ability to intuitively explore data to find meaning and patterns more efficiently. Interactivity, however, becomes progressively more difficult as the size of the dataset increases. This project begins by leveraging existing web-based data visualization technologies and extends their functionality through the use of parallel processing. This methodology utilizes state-of-the-art techniques, such as Node.js, to split the visualization rendering and user interactivity controls between a client-server infrastructure. The approach minimizes data transfer by performing the rendering step on the server while allowing for the use of HPC systems to render the visualizations more quickly. In order to improve the scaling of the system with larger datasets, parallel processing and visualization optimization techniques are used.

MS, University of Cincinnati, 2014, Engineering and Applied Science: Computer Engineering

Transactional memory is a concurrency control mechanism that dynamically determines when threads may safely execute critical sections of code. It does so by tracking memory accesses performed within a transactional region, or critical section, and detecting when memory operations conflict with other threads. Transactional memory provides the performance of fine-grained locking mechanisms with the simplicity of coarse-grained locking mechanisms. Parallel Discrete Event Simulation is a problem space that has been studied for many years, but still suffers from significant lock contention on SMP platforms. The pending event set is a crucial element to PDES, and its management is critical to simulation performance. This is especially true for optimistically synchronized PDES, such as those implementing the Time Warp protocol. Rather than prevent causality errors, events are aggressively scheduled and executed until a causality error is detected. This thesis explores the use of transactional memory as an alternative to conventional synchronization mechanisms for managing the pending event set in a time warp synchronized parallel simulator. In particular, this thesis examines the use of Intel's hardware transactional memory, TSX, to manage shared access to the pending event set by the simulation threads. In conjunction with transactional memory, other solutions to contention are explored such as the use of multiple queues to hold the pending event set and the dynamic binding of threads to these multiple queues. For each configuration a comparison between conventional locking mechanisms and transactional memory access is performed to evaluate each within the WARPED parallel simulation kernel. In this testing, evaluation of both forms of transactional memory (HLE and RTM) implemented in the Haswell architecture were performed. The results show that RTM generally outperforms conventional locking mechanisms and that HLE provides consistently better performance tha (open full item for complete abstract)

MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering

LlamaOS is a custom operating system that provides much of the basic functionality needed for low latency applications. It is designed to run in a Xen-based virtual machine on a Beowulf cluster of multi/many-core processors. The software architecture of llamaOS is decomposed into two main components, namely: the llamaNET driver and llamaApps. The llamaNET driver contains Ethernet drivers and manages all node-to-node communications between user application programs that are contained within a llamaApp instance. Typically, each node of the Beowulf cluster will run one instance of the llamaNET driver with one or more llamaApps bound to parallel applicaitons. These capabilities provide a solid foundation for the deployment of MPI applications as evidenced by our initial benchmarks and case studies. However, a message passing standard still needed to be either ported or implemented in llamaOS. To minimize latency, llamaMPI was developed as a new implementation of the Message Passing Interface (MPI), which is compliant with the core MPI functionality. This provides a standardized and easy way to develop for this new system. Performance assessment of llamaMPI was achieved using both standard parallel computing benchmarks and a locally (but independently) developed program that executes parallel discrete event-driven simulations. In particular, the NAS Parallel Benchmarks are used to show the performance characteristics of llamaMPI. In the experiments, most of the NAS Parallel Benchmarks ran faster than, or equal to their native performance. The benefit of llamaMPI was also shown with the fine-grained parallel application WARPED. The order of magnitude lower communication latency in llamaMPI greatly reduced the amount of time that the simulation spent in rollbacks. This resulted in an overall faster and more efficient computation, because less time was spent off the critical path due to causality errors.

Doctor of Philosophy (PhD), Wright State University, 2007, Engineering PhD

Design of the next generation of ion engines can benefit from detailed computer simulations of the plasma in the discharge chamber. In this work a complete particle based approach has been taken to model the discharge chamber plasma.This is the first time that simplifying continuum assumptions on the particle motion have not been made in a discharge chamber model. Because of the long mean free paths of the particles in the discharge chamber continuum models are questionable. The PIC-MCC model developed in this work tracks following particles: neutrals, singly charged ions, doubly charged ions, secondary electrons, and primary electrons. The trajectories of these particles are determined using the Newton-Lorentz's equation of motion including the effects of magnetic and electric fields. Particle collisions are determined using an MCC statistical technique. A large number of collision processes and particle wall interactions are included in the model. The magnetic fields produced by the permanent magnets are determined using Maxwell's equations. The electric fields are determined using an approximate input electric field coupled with a dynamic determination of the electric fields caused by the charged particles. In this work inclusion of the dynamic electric field calculation is made possible by using an inflated plasma permittivity value in the Poisson solver. This allows dynamic electric field calculation with minimal computational requirements in terms of both computer memory and run time. In addition, a number of other numerical procedures such as parallel processing have been implemented to shorten the computational time. The primary results are those modeling the discharge chamber of NASA's NSTAR ion engine at its full operating power. Convergence of numerical results such as total number of particles inside the discharge chamber, average energy of the plasma particles, discharge current, beam current and beam efficiency are obtained. Steady state results for th (open full item for complete abstract)

MS, University of Cincinnati, 2004, Engineering : Computer Science

Characterizing the dynamic behavior of parallel programs in terms of their execution profile helps to understand their behavior and suggest optimization strategies to improve the performance. Traditional event tracing techniques write the data obtained by profiling to trace files. Using the traditional approach for fine-grained profiling not only yields large unwieldy trace files but often also gives skewed results due to the inaccuracies introduced by the profiling since the data is written to files. Current efforts in profiling research are directed towards understanding ways to reduce execution times by performing online profiling and using the data thus obtained to drive performance steering systems. This thesis describes an efficient and fast approach to profile parallel programs at a very fine level of granularity by measuring performance metrics at the level of each data element. The approach is implemented as a tool named ‘Chiffon' that provides a simple API for source code instrumentation to enable fine-grained profiling at the level of individual mesh element. The tool generates traces of profiled data compacted in space and sampled in time. The goals of this thesis are to develop an efficient way to profile mesh-based parallel applications so that the profile data can be used to develop a workload generator that simulates the parallel program and to enable online profiling of the parallel application for runtime optimization. The approach described in this paper is novel in that profile data is associated with data elements not processors, so the profile data can be used, for ex ample, to develop adaptive loadbalancing policies. Experimental results discussing the parameters affecting the quality, speed and overhead of the approach are presented.

Doctor of Philosophy in Engineering, University of Toledo, 2004, Electrical Engineering

A new class of intelligent adaptive control for systems with complex and multimodal dynamics including scheduled and unscheduled ‘Jumps', is developed. Those systems are often under the challenge of unforeseen changes due to wide range of operations and/or external influences. The underlying structural feature is an introduction of an Intelligent Supervisory Loop (ISL) to augment the Model Reference Adaptive Control (MRAC) framework. Four novel design formulations are developed which evolve from different methods of conceiving ISL, structured into intelligent control algorithms, and then investigated with comprehensive simulation models of a single link flexible robotic manipulator as well as a six degree of freedom F16 fighter aircraft. The first scheme is a Fuzzy Multiple Reference Model Adaptive Controller (FMRMAC). It consists of a fuzzy logic switching strategy introduced to the MRAC framework. The second is a novel Neural Network Parallel Adaptive Controller (NNPAC) for systems with unmodeled dynamics and mode swings. It consists of an online growing dynamic radial basis neural network, which controls the plant in parallel with a direct MRAC. The third scheme is a novel Neural Network Parallel Fuzzy Adaptive Controller (NNPFAC) for dynamic ‘Jump' systems showing scheduled mode switching and unmodeled dynamics. The scheme consists of a growing online dynamic Neural Network (NN) controller in parallel with a direct MRAC, and a fuzzy multiple reference model generator. The fourth scheme is a Composite Parallel Multiple Reference Model Adaptive Controller (CPMRMAC) for systems showing unscheduled mode switching and unmodeled dynamics. The scheme consists of an online growing dynamic NN controller in parallel with a direct MRAC, and an NN multiple reference model generator. Extensive feasibility simulation studies and investigations have been conducted on the four proposed schemes, and with results consistently showing that the four design formulations developed in (open full item for complete abstract)

Master of Science, The Ohio State University, 2012, Electrical and Computer Engineering

The Meddis MATLAB Auditory Periphery (MAP) model is a computational model of the mammalian auditory system made using MATLAB. The model simulates the physiological processes taking place at different stages within the auditory system and provides an insight on how a sound wave incident on the ear is modified as it passes through the auditory system. The stages of the auditory system included in the model are the middle ear, the inner ear and parts of the brain stem. Calculating the response of each stage is a computationally intensive and time consuming task. It takes more than 7 minutes to just calculate the response of all auditory nerves, each producing an action potential about 300 times a second for a sound signal of 1 second duration when 1000 best frequencies are considered. This is a major disadvantage especially when the model has to be run multiple times in speech and hearing experiments. The thesis describes how the runtime of the MAP model can be reduced by modifying the code, enabling it to run in parallel on multiple processing cores using tools provided by MATLAB. The thesis also describes how GPUs can be utilized to further reduce runtimes. The thesis concludes with an application of the MAP model in detecting differences between FM signals.

Master of Science, The Ohio State University, 2011, Computer Science and Engineering

We investigate the parallelization of an algorithm on three very different architectures. These are: a 128-processor Cray XMT massively multithreaded machine, a 16-processor IBM x3755 shared memory machine and a 240-core NVIDIA FX 5800 graphics processor unit (GPU). The problem we use in our investigation is the well-known subset-sum problem. While this is known to be NP-complete, it is solvable in pseudo-polynomial time, i.e., time proportional to the number of input objects multiplied by the sum of their sizes. This product defines the size of the dynamic programming table used to solve the problem. The hypothesis that we wish to test is that the Cray, with its specialized hardware and large uniform shared memory, is suitable for very large problems, the IBM x3755 is suitable for intermediate sized problems and the NVIDIA FX 5800 can give superior performance only for problems that fit within its modest internal memory. We show that it is straightforward to parallelize this algorithm on the Cray XMT primarily because of the word-level locking that is available on this architecture. For the other two machines we present an alternating word algorithm that can implement an efficient solution. The timings of our respective codes were carefully measured over a comprehensive range of problem sizes. On the Cray XMT we observe very good scaling for large problems and see sustained performance as the problem size increases. However this machine has poor scaling for small problem sizes; it performs best for problem sizes of 1012 bits or more. The IBM x3755 performs very well on medium sized problems, but has poor scalability as the number of processors increases and is unable to sustain performance as the problem size increases. This machine tends to saturate for problem sizes of 1011 bits. The NVIDIA GPU performs well for problems whose tables t within its 4GB device memory. This corresponds to tables of size approximately 1010/. The experimental measurements support ou (open full item for complete abstract)

Master of Science, The Ohio State University, 2010, Computer Science and Engineering

Data mining has emerged as an important class of high performance applications. At the same time, most parallel platforms today are clusters of multi-core machines. Thus, one of the major challenges today is achieving programmability and performance for data mining applications on multi-core machines and cluster of multi-core machines. FREERIDE (FRamework for Rapid Implementation of Datamining Engines) is a middleware developed based on the observation that the processing structure of a large number of data mining algorithms involves generalized reductions. FREERIDE offers a high-level interface and implements both distributed memory and shared memory parallelization. In this thesis, theWavelet Transformation algorithm is considered and it is shown how it can be modeled as a generalized reduction structure. It is parallelized using the FREERIDE middleware. It is shown that the algorithm can be parallelized in a communication and storage efficient manner. By this method, a good parallel efficiency with a speedup of around 42 on 64 cores is achieved. The second algorithm considered is a challenging new data mining algorithm, information theoretic co-clustering. This algorithm is parallelized using FREERIDE middleware. It is shown that the main processing loops of row clustering and column clustering of the the Co-clustering algorithm essentially fit into a generalized reduction structure. A good parallel efficiency is achieved and a speedup of nearly 21 is reported on 32 cores.

Master of Science (MS), Ohio University, 2008, Mechanical Engineering (Engineering and Technology)

The Three Cable Haptic Interface (TCHI) prototype built by Williams et. al (2006) is improved by selecting and installing appropriate motors and designing cable reels which together successfully provided the proper amount of force for the intended application.Simulation was performed which showed that the required cable tension force rises almost linearly with frame size, but rises exponentially as the distance from the base plane (Y distance) decreases. Furthermore, it was determined from simulation that the required cable tension can be significantly lessened if the device is configured in such a way as to limited the workspace to approximately 6 cm from the top and sides and 13 cm from the imaginary diagonal which spans from top right motor to bottom left. The new TCHI prototype is theoretically able to exert 31N of continuous force on the user, a 10 fold improvement over the PHANToM 3.0 and has a nominal position resolution of 0.004mm, a 5 fold improvement over the PHANToM 3.0. The new TCHI prototype is also superior to the PHANToM 3.0 in terms of maximum exertable force, stiffness, cost, and workspace if configured properly.

Master of Science, Miami University, 2009, Computer Science and Systems Analysis

Realizing the advantages of simulation-based methodologies requires the use of a software environment that is conducive for modeling, simulation, and analysis. Furthermore, parallel simulation methods must be employed to reduce the time for simulation, particularly for large problems, to enable analysis in reasonable timeframes. Accordingly, this thesis covers the development of a general purpose agent-based, parallel simulation environment called MUSE (Miami University Simulation Environment). MUSE, provides an Application Program Interface (API) for agent-based modeling and a framework for parallel simulation. The API was developed in C++ using its object oriented features. The core parallel simulation capabilities of MUSE were realized using the Time Warp synchronization methodology and the Message Passing Interface (MPI). Experiments show MUSE to be a scalable and efficient simulation environment.

Master of Science (MS), Ohio University, 2013, Mechanical Engineering (Engineering and Technology)

The purpose of this thesis is to evaluate a three degree of freedom (DOF) revolute-spherical-revolute (RSR) configured robotic manipulator for the use of controlling yaw, pitch, and roll of a model aircraft. Studies of past 3-DOF parallel manipulators were used to gain an understanding of how to design such a system without creating singularity conditions. Inverse orientation and forward orientation kinematics were derived from the vector loop closure equation of the system. This study investigated what effects would occur to the maximal rotational capabilities of the robotic system when the constant lengths of the parallel manipulator were changed. It was determined that the IOK and FOK solutions of the system were valid and that such a system would be able to attain requested angular rotations by the aircraft's team. However, modeling of the system led to a case were another leg configuration wanted to be used, as it proved to reduce the torque applied to the servo motors within the system. A prototype of the new parallel manipulator was machined and future work on this project will require the derivation of the kinematics equations, such as was done with the 3-RSR orientation.

PHD, Kent State University, 2025, College of Arts and Sciences / Department of Modern and Classical Language Studies

Corpus-based approaches have seen substantial growth across different areas of applied translation studies, with translator pedagogy emerging as a key area of focus. This is evident in the broad range of academic literature, alongside the current ongoing projects, dedicated to this field. While considerable research has already examined the role of different corpus types in translator education, relatively little has been done with parallel corpora to empirically validate the underlying assumptions reviewed in the literature, particularly in terms of English-Arabic translation. This study seeks to bridge this gap by conducting a more systematic and empirical investigation of parallel corpus-based translation teaching (PCBT), taking into account two primary areas of enquiry: 1) if and how the incorporation of parallel corpora has an impact on the quality of student translations, and 2) if and how students find this approach conducive to learning to translate. Student translations and survey responses were analyzed to gain insight into the effectiveness of PCBT. The findings reveal that PCBT has led to an improvement in translation quality, as seen in its capacity to mitigate error occurrences in student translations. Furthermore, the findings point to the potential of PCBT in fostering more constructive learning through students' engagement in data-driven learning, a process that included observation, negotiation, evaluation, and critical thinking. Finally, the responses from the survey demonstrate that the students exhibited positive attitudes toward PCBT, recognizing its impact not only in terms of improving their translation accuracy and quality but also in terms of reinforcing positive attitudes toward translation.

Doctor of Philosophy (Ph.D.), University of Dayton, 2024, Electro-Optics

Traditionally, spectrometers characterize the steady-state conditions of spectral signatures of materials ranging from short ultraviolet to near infrared wavelengths, mainly because linear CCD arrays are easily manufacturable for the visible wavelength region while mid and long-wave infrared linear arrays are prohibitively costly. Moreover, a big constraint on the charge coupled or CMOS detectors is the refresh rate limit. Since the detector array device serializes captured parallel data, bandwidth is strongly limited. The usual charge-discharge period of commercial products that are used inside the spectrometers is on average 8.3ms. In specific areas of research, such as dynamic or high-speed phase change materials or fast biological processes, real-time effects carry useful information and 8.3ms time range is considered as steady-state. Current state of the art spectrometers could potentially use pump-probe techniques to overcome the speed problem, although that comes at the expense of extensive exposure to pump-pulses which might not be feasible, such as in the case for irreversible processes. This dissertation proposes a new step towards real-time dynamic spectroscopy using electro-optical engineering techniques to solve speed and wavelength trade-off. In this dissertation, a new type of ultrafast spectrometer based on high-speed, low-noise electronics, fiber optics, and supercontinuum light sources is proposed to solve the bottlenecks associated with traditional spectroscopy techniques, showing a viable path toward GHz-speed spectroscopy capable of characterizing dynamic materials at the sub-nanosecond time scales.

Master of Science, The Ohio State University, 2006, Graduate School