Master of Science in Engineering (MSEgr), Wright State University, 2006, Electrical Engineering

For the process of converting low-power digital signals into their high-power analog counterparts, the functions of digital-to-analog conversion (at low power) and analog power amplification are separately implemented. This thesis proposes a new “STAC-DAC” circuit topology which directly realizes high-power analog output from low-power digital input signals. The ability to achieve a “direct from digital” high-power analog output in a single high-efficient, low-distortion design has significant potential in audio reproduction, and flexible signal generation applications. In this thesis, the “STAC-DAC” is described and its implementation via MATLAB and LTSpice is discussed. The results of simulations are used to prove the concept of the design. The 16-bit design features a high-power output of 100 watts or more at an efficiency of 93%. The design is optimized to feature low total harmonic distortion (THD) of 0.055% for a 1 kHz signal at 100 watts into an 8 Ω load and low phase distortion of less than 10° for a 20 kHz signal and only 1° at 1 kHz. The “STAC-DAC” design is applicable to any design which requires a high-power analog output that is controlled by a logic level digital input. The results validated that the “STAC-DAC” can produce low-level THD figures over the audio frequency range. If very low THD figures are not necessary, high-power analog operation can be achieved into the hundreds of kilohertz while maintaining high efficiency. These results show that the power “STAC-DAC” is capable of simultaneously achieving the highly efficient circuitry associated with digital-to-analog converters with the low harmonic and phase distortion requirements associated with high fidelity analog audio amplifiers.

Committee: Marian Kazimierczuk (Advisor) Subjects:

Doctor of Philosophy, University of Akron, 2018, Electrical Engineering

This work presents a fully-integrated multi-sensor system based on CMOS technology that contains pH, electrical conductivity (EC), and temperature sensors, as well as an extended-counting analog-to-digital converter (EC-ADC). The pH sensor is implemented using an ion-sensitive field-effect transistor (ISFET) where two low-power, compact pH readout circuits have been designed to overcome the nonidealities of ISFETs. In addition, a novel electrode structure for the EC sensor has been implemented, which eliminates the conventional post-processing steps, thus reducing the cost and fabrication difficulties. Using different frequencies generated by a variable frequency oscillator, the detection range of the proposed EC sensor spans three orders of magnitude, from 20 µS/cm to 10 mS/cm. Furthermore, a complementary to absolute temperature (CTAT) current source with diode-connected transistors was used as the temperature sensor. The measurement range is from 18◦C to 35◦C. The core area, including all three sensors and readout circuits is 2.1 mm2. The EC-ADC is a combination of an incremental sigma-delta and a time-mode ADC. By sharing the OTA and the comparator between two ADCs, the implemented circuit allows the smallest core area amongst state-of-the-art ADCs with similar resolution and bandwidth. The core area of the proposed ADC is 0.0625 mm2, and the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.4/-0.4 and +0.84/-0.88 LSB, respectively.

Committee: Kye-shin Lee Dr. (Advisor); Joan E. Carletta Dr. (Committee Member); Ryan C. Toonen Dr. (Committee Member); Truyen Van Nguyen Dr. (Committee Member); Chelsea Monty Dr. (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 2012, Electrical and Computer Engineering

The Linearization of power ampliers is a research area of growing importance. Among the many approaches which have been tried, digital predistortion (DPD)remain, one of the most promising techniques. In this thesis, a new generalized frequency-selective DPD technique is investigated. The proposed linearization algorithm is signal independent and any band limited signal can be linearized. 3rd and 5th order linearizations are demonstrated using various multi-tone signals. For 3rd order linearization, more than 15 dB cancellation for the inband distortion, 14 dB cancellation on 3rd order interband intermodulation distortion (IMD) were achieved. For the 5th order linearization, more than 15 dB IMD cancellation on inband, 16 dB cancellation on the 3rd order interband IMD, and 6 dB on 5th order interband IMD cancellation were achieved. To demonstrate the applicability of the algorithm to multiple bands, the two-band theory was modied to a three-band theory with up to 3rd order compensation. In the three-band case, the interband linearization played an important role in the overall performance. Without the interband linearization, only 3-4 dB IMD cancellation was observed. However, with interband compensation, more than 10 dB IMD cancellation was achieved. For the three-band case, to investigate the robustness of the DPD system, the middle channel was turned off and the same coefficients worked well for two bands. In recent DPD applications, the linearization of largely spaced two-band signals have generated a lot of interest. In this work, the same algorithm was applied to 250 MHz spaced signal and more than 15 dB IMD cancellation was achieved. For the signal separation, a digital IF technique was proposed which uses only a single local oscillator (LO) for synthesizing the band separation. Previous works used two dierent LOs for the signal generation using expensive commercial synthesizers. In this work, a low cost testbed consisting of a field programmable gate array (open full item for complete abstract)

Committee: Patrick Roblin PhD (Advisor); Furrukh Khan PhD (Committee Member); Joanne DeGroat PhD (Committee Member) Subjects: Electrical Engineering