MS, University of Cincinnati, 2023, Education, Criminal Justice, and Human Services: Information Technology

The University of Cincinnati's Advanced Research Computing Center employs effective ways through this study in order to make the High-Performance Computing Cluster accessible across all disciplines on campus and the Cincinnati Innovation District. To understand the needs of our users, we employed Norman Nielsen's Group principles of conducting a usability study which involved a survey and think-aloud activity to draw a cognitive understanding of our participants expectations while performing basic tasks and conducted a heuristic evaluation to rate the severity of issues participants identified. Our findings which gave a high-level understanding of how the HPC Cluster can be made more accessible across all disciplines regardless of the user's technical skills, involved the need to build a customized graphical user interface HPC management portal to serve users' needs.Also, investing in workforce development by introducing an academic credit-based High-Performance Computing Course for students and partnering with other faculty's to introduce special programs, e.g. Student Cluster Competitions which would draw more student interest.

Committee: Jess Kropczynski Ph.D. (Committee Chair); Amy Latessa Ph.D. (Committee Member); Shane Halse Ph.D. (Committee Member) Subjects: Information Technology

Master of Science (MS), Bowling Green State University, 2015, Computer Science

Benefits of Cloud Computing (CC) such as scalability, reliability, and resource pooling have attracted scientists to deploy their High Performance Computing (HPC) applications on the Cloud. Nevertheless, HPC applications can face serious challenges on the cloud that could undermine the gained benefit, if care is not taken. This thesis targets to address the shortcomings of the Cloud for the HPC applications through a platform called HPC as a Service (HPCaaS). Further, a novel scheme is introduced to improve the performance of HPC task scheduling on the Cloud using the emerging technology of Software-Defined Networking (SDN). The research introduces “ASETS: A SDN-Empowered Task Scheduling System” as an elastic platform for scheduling HPC tasks on the cloud. In addition, a novel algorithm called SETSA is developed as part of the ASETS architecture to manage the scheduling task of the HPCaaS platform. The platform monitors the network bandwidths to take advantage of the changes when submitting tasks to the virtual machines. The experiments and benchmarking of HPC applications on the Cloud identified the virtualization overhead, cloud networking, and cloud multi-tenancy as the primary shortcomings of the cloud for HPC applications. A private Cloud Test Bed (CTB) was set up to evaluate the capabilities of ASETS and SETSA in addressing such problems. Subsequently, Amazon AWS public cloud was used to assess the scalability of the proposed systems. The obtained results of ASETS and SETSA on both private and public cloud indicate significant performance improvement of HPC applications can be achieved. Furthermore, the results suggest that proposed system is beneficial both to the cloud service providers and the users since ASETS performs better the degree of multi-tenancy increases. The thesis also proposes SETSAW (SETSA Window) as an improved version of SETSA algorism. Unlike other proposed solutions for HPCaaS which have either optimized the cloud to make it more HPC-fr (open full item for complete abstract)

Committee: Hassan Rajaei Ph.D (Advisor); Robert Green Ph.D (Committee Member); Jong Kwan Lee Ph.D (Committee Member) Subjects: Computer Engineering; Computer Science; Technology

MS, University of Cincinnati, 2002, Engineering : Computer Engineering

The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed in the Digital Design Environments Laboratory at the University of Cincinnati. iPACE-V1 was specifically designed for real time, in-field image processing applications. Adaptive computing systems can be broadly defined as those systems which can modify their digital hardware to match the requirements of an application at hand. Field Programmable Gate Arrays (FPGA) are essential building blocks of such systems. iPACE-V1 has three Xilinx Virtex FPGAs: one houses the controller module, another acts as the main user programmable module and the data capture module is implemented in the last one. A maximum of 800,000 logic gates are available for computing in the form of FPGAs. Furthermore, 4 Mbytes of ZBT (Zero Bus turnaround) SRAM is interfaced. In addition to this, the board has a maximum of 1 Gigabytes SDRAM capacity. For non volatile data storage we have provided 4 Mbytes of FLASH ROM. Two serial ports along with a USB port are also provided. A camera is attached which provides video data and a small LCD is interfaced for image output. Every effort was made to incorporate as many debugging features, as possible: programmable clock, observable memories, partial reconfiguration and FPGA read-back are some features which top this list. Several controller cores have been written for various subsystems in iPACE-V1. These cores enable the user to efficiently exploit the available resources. This thesis discusses the hardware architecture of iPACE-V1 along with the VHDL controller cores. We also show the functional correctness and effectiveness of iPACE-V1. We have developed two demonstration examples for iPACE-V1: A frame grabber and a background elimination application. The frame grabber is implemented to demonstrate the functional correctness of the hardware. Whereas, the background elimination application is more performance oriented and is used to show th (open full item for complete abstract)

Committee: Dr. Ranga Vemuri (Advisor) Subjects: Computer Science

Master of Science, The Ohio State University, 2012, Electrical and Computer Engineering

The Meddis MATLAB Auditory Periphery (MAP) model is a computational model of the mammalian auditory system made using MATLAB. The model simulates the physiological processes taking place at different stages within the auditory system and provides an insight on how a sound wave incident on the ear is modified as it passes through the auditory system. The stages of the auditory system included in the model are the middle ear, the inner ear and parts of the brain stem. Calculating the response of each stage is a computationally intensive and time consuming task. It takes more than 7 minutes to just calculate the response of all auditory nerves, each producing an action potential about 300 times a second for a sound signal of 1 second duration when 1000 best frequencies are considered. This is a major disadvantage especially when the model has to be run multiple times in speech and hearing experiments. The thesis describes how the runtime of the MAP model can be reduced by modifying the code, enabling it to run in parallel on multiple processing cores using tools provided by MATLAB. The thesis also describes how GPUs can be utilized to further reduce runtimes. The thesis concludes with an application of the MAP model in detecting differences between FM signals.

Committee: Ashok Krishnamurthy PhD (Advisor); Yuan Zheng PhD (Committee Member); Lawrence Feth PhD (Committee Member) Subjects:

Master of Science, The Ohio State University, 2011, Computer Science and Engineering

Distributing spatially located heterogeneous workloads is an important problem in parallel scientific computing. Particle-in-cell simulators, ray tracing and partial differential equations are some of the applications with spatially located workload. We investigate the problem of partitioning such workloads (represented as a matrix of non-negative integers) into rectangles, such that the load of the most loaded rectangle (processor) is minimized. Since finding the optimal arbitrary rectangle-based partition is an NP-hard problem, we investigate particular classes of solutions: rectilinear, jagged and hierarchical. We present a new class of solutions called m-way jagged partitions, propose new optimal algorithms for m-way jagged partitions and hierarchical partitions, propose new heuristic algorithms, and provide worst case performance analyses for some existing and new heuristics. Balancing the load does not guarantee to minimize the total runtime of an application. In order to achieve that, one must also take into account the communication cost. Rectangle shaped partitioning inherently keeps communications small, yet one should proactively minimize them. The algorithms we propose are tested in simulation on a wide set of instances and compared to state of the art algorithm. Results show that m-way jagged partitions are low in total communication cost and practical to use.

Committee: Umit V. Catalyurek PhD (Advisor); Radu Teodorescu PhD (Committee Member) Subjects: Computer Science

Master of Science (MS), Bowling Green State University, 2011, Computer Science

With the rapid growth of Cloud Computing, the use of Clouds in educational settings can provide great opportunities for Computer Science students to improve their learning outcomes. In this thesis, we introduce Cloud-Based Education architecture (CBE) as well as Cloud-Based Education for Computer Science (CBE-CS) and propose an automated CBE-CS ecosystem for implementation. This research employs the Cloud as a learning environment for teaching Computer Science courses by removing the locality constraints, while simultaneously improving students' understanding of the material provided through practical experience with the finer details and subjects' complexities. In addition, this study includes a comparison between Cloud-based virtual classrooms and the traditional e-learning system to highlight the advantages of using Clouds in such a setting. We argue that by deploying Computer Science courses on the Cloud, the institution, administrators, faculty, and the students would gain significant advantages from the new educational setting. The infrastructure buildup, the software updating and licenses managements, the hardware configurations, the infrastructure space, maintenance, and power consumption, and many other issues will be either eliminated or minimized using the Cloud technology. On the other hand, the number of enrolled students is likely to increase since the Cloud will increase the availability of the needed resources for interactive education of larger number of students; it can deliver advanced technology for hands-on training, and can increase the readiness of the students for job market. The CBE-CS approach is more likely to allow faculty to better demonstrate the subjects' complexities to the students by renting he needed facilities whenever it is desired. The research also identified several potential Computer Science courses which could be launched and taught through Clouds. In addition, the selected courses have been classified based on three well- (open full item for complete abstract)

Committee: Hassan Rajaei PhD (Advisor); Guy Zimmerman PhD (Committee Member); Jong Lee PhD (Committee Member) Subjects: Computer Science

MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering

DNA computing is a new and interesting development that connects computer science to molecular biology. The idea of DNA computing arose from Adleman's 1994 experiment in which he showed how to solve the Hamiltonian path problem (HPP) in polynomial time using oligonucleotides of DNA. DNA computing enables massive parallelism at the molecular level and is one of the technologies being explored by researchers as a supplement to traditional silicon-based computing. But many computer scientists and computer engineers have little knowledge of biology and therefore find it difficult to get started in the field of DNA computing. Thus the aim of this work is to provide a tutorial to introduce DNA computing to a wider audience and to show some examples of how DNA computing can be simulated using agent-based techniques and can be applied to solve complex problems. Currently our system consists of four sections: DNA structure and behavior, basic DNA computation, DNA-based cryptography, and using agent based modeling and simulation to explore DNA behavior. We also provide a small assessment test to enable users to test themselves and evaluate their knowledge of the topics covered. The system is modular in design and can easily be modified or extended to include more information on each topic or to include additional examples of DNA computing.

Committee: Carla Purdy Ph.D. (Committee Chair); George Purdy Ph.D. (Committee Member); Anca Ralescu Ph.D. (Committee Member) Subjects: Computer Engineering

Master of Science in Computer Engineering, University of Dayton, 2024, Engineering

The work outlined here seeks to address the issue of detection and tracking of a moving object using a moving Event-Based Sensor (EBS) camera. Others have solved this issue by using power-hungry Convolutional Neural Networks (CNNs) which negate the low Size, Weight, And Power (SWAP) and high-speed benefits of an EBS camera. Throughout this paper, an attempt is made to solve the detection and tracking problem while keeping the low SWAP benefits of the EBS camera. This starts by looking at lightweight stationary EBS tracking algorithms and applying neuromorphic and hyperdimensional computing approaches to optimize the storage and runtime of the software. Ultimately, it was determined that the original approach was more time-efficient and therefore was used as a starting point for the Moving Sensor Moving Object (MSMO) detection and tracking algorithm. The MSMO algorithm uses the velocities of each event to create an average of the scene and filter out dissimilar events. This work shows the study performed on the velocity values of the events and explains why ultimately an average-based velocity filter is insufficient for lightweight MSMO detection and tracking of objects using an EBS camera.

Committee: Tarek Taha Dr. (Committee Chair); Christopher Yakopcic Dr. (Committee Member); Eric Balster Dr. (Committee Member) Subjects: Computer Engineering

Master of Science in Mathematics, Youngstown State University, 2023, Department of Mathematics and Statistics

A graph G is said to arrow a graph H if every red-blue edge coloring of G presents a monochromatic H, and is written G→H. The down-arrow Ramsey set reports all subgraphs H of a graph G for which G→H. Formally, the down-arrow Ramsey set is a graph G is ↓G:= {H⊆G: G→H }. Calculating this set by way of scientific computing is computationally prohibitive with the resources commonly available to graph theorists and other academics. Using existing research into complete graphs, the down-arrow Ramsey sets for small complete graphs (Kn for 2 ≤ n ≤ 7) can be generated quickly. For larger complete graphs (Kn for 8 ≤ n ≤ 11) specific pre-processing steps are leveraged to speed up calculations in addition to existing data sets. Presented is work on the development of a Python script to generate the down-arrow Ramsey set of a graph through efficient memory management and parallel computing methodologies. The down-arrow generator is used to report new results on complete graphs as well as complete bipartite graphs, and assorted other graphs.

Committee: Alexis Byers PhD (Advisor); Alina Lazar PhD (Committee Member); Anita O'Mellan PhD (Committee Member) Subjects: Computer Science; Mathematics

Master of Science (MS), Wright State University, 2022, Computer Science

Motivational Interviewing (MI) is an evidence-based brief interventional technique that has been demonstrated to be effective in triggering behavior change in patients. To facilitate behavior change, healthcare practitioners adopt a nonconfrontational, empathetic dialogic style, a core component of MI. Despite its advantages, MI has been severely underutilized mainly due to the cognitive overload on the part of the MI dialogue evaluator, who has to assess MI dialogue in real-time and calculate MI characteristic metrics (number of open-ended questions, close-ended questions, reflection, and scale-based sentences) for immediate post-session evaluation both in MI training and clinical settings. To automate dialogue assessment and produce instantaneous feedback several technology-assisted MI (TAMI) tools like ReadMI based on Natural Language Processing (NLP) have been developed on mobile computing platforms like Android. These tools, however, are ill-equipped to support remote work and education settings, a consequence of the COVID-19 pandemic. Furthermore, these tools lack data visualization features to intuitively understand and track MI progress. In this thesis, to address the aforementioned shortcomings in the current landscape of TAMI, a web-based MI data visualization dashboard tool ReadMI.org has been designed and developed. The proposed dashboard leverages the highperformance computing capacity of cloud-based Amazon Web Service (AWS) to implement the NLP-based dialogue assessment functionality of ReadMI and a vibrant data visualization capability to intuitively understand and track MI progress. Additionally, through a simple Uniform Resource Locator (URL) address, ReadMI.org allows MI practitioners and trainers to access the proposed dashboard anywhere and anytime. Therefore, by leveraging the high-performance computing and distribution capability of cloud computing services, ReadMI.org has the potential to reach the growing population of MI practitioner (open full item for complete abstract)

Committee: Ashutosh Shivakumar Ph.D. (Committee Chair); Yong Pei Ph.D. (Committee Co-Chair); Thomas Wischgoll Ph.D. (Committee Member); Paul J. Hershberger Ph.D. (Committee Member) Subjects: Behavioral Psychology; Computer Engineering; Computer Science

Doctor of Philosophy (PhD), Ohio University, 2022, Electrical Engineering & Computer Science (Engineering and Technology)

Improvements from electronic processor and interconnect performance scaling are narrowing due to fundamental challenges faced at the device level. Compounding the issue, increasing demand for large, accurate deep neural network models has placed significant pressure on the current generation of processors. The slowing of Moore's law and the breakdown of Dennard scaling leaves no room for innovative solutions in traditional digital architectures to meet this demand. To address these scaling issues, architectures have moved away from general-purpose computation towards fixed-function hardware accelerators to handle demanding computation. Although electronic accelerators alleviate some of the pressure of deep neural network workloads, they are still burdened by electronic device and interconnect scaling problems. There is potential to further scale computer architectures by utilizing emerging technology, such as photonics. The low-loss interconnects and energy-efficient modulators provided by photonics could help drive future performance scaling. This could innovate the next generation of high-bandwidth, bandwidth-dense interconnects, and high-speed, energy-efficient processors by taking advantage of the inherent parallelism of light. This dissertation investigates photonic architectures for communication and computation acceleration to meet the machine learning processing requirements of future systems. The benefits of photonics is explored for bit-level parallelism, data-level parallelism, and in-network computation. The research performed in this dissertation shows that photonics has the4 potential to enable the next generation of deep neural network application performance by improving energy-efficiency and reducing compute latency. The evaluations in this dissertation conclude that photonic accelerators can: (1) Reduce energy-delay product by 73.9% at the bit-level on convolutional neural network workloads; (2) Improve throughput by 110× (open full item for complete abstract)

Committee: Avinash Karanth (Advisor) Subjects: Computer Engineering; Computer Science; Electrical Engineering

PhD, University of Cincinnati, 2022, Engineering and Applied Science: Computer Science and Engineering

The work shown in this study demonstrates how Evolutionary Computing (EC) can be used to add trust to Hardware Design Language (HDL) Intellectual Property (IP). HDL IP is often obtained through a 3rd party source due to time and cost constraints, in turn the IP is then considered untrusted by designers. These 3rd party IP could be infected with malicious additions, like Hardware Trojans (HT), or other damaging modifications. HT can often go undetected through standard detection techniques, but even if a designer can identify that there is something wrong with their design, how do they go about repairing it? We propose a study to investigate the ability to remove HT, investigate the use of partial test cases for evolution, and comment on the scalability of the approach. The authors then propose PyGenP, a Genetic Programming (GP) network written in Python, that allows for fast and quick evolution of HDL programs. A Hybrid Memetic GP algorithms that modify the population initialization function is then shown to offer an improvement over traditional GP, while generating better low-order schemas. Finally, we propose an algorithm, using this Hybrid Memetic Genetic Programming initialization function, to perform Targeted Evolution, on select portions of am HDL program, and comment on the improvements the algorithm offers over traditional GP. The authors then close by giving a retrospect of the work completed, and offer recommendations for future work.

Committee: Rashmi Jha Ph.D. (Committee Member); John Gallagher Ph.D. (Committee Member); Temesguen Messay Kebede Ph.D. (Committee Member); David Kapp PhD (Committee Member); Wen-Ben Jone Ph.D. (Committee Member) Subjects: Computer Science

Doctor of Philosophy, The Ohio State University, 2020, Computer Science and Engineering

Replication has been a cornerstone of reliable distributed storage systems for years. Replicating data at multiple locations in the system maintains sufficient redundancy to tolerate individual failures. However, the exploding volume and speed of data growth let researchers and engineers think about using storage-efficient fault tolerance mechanisms to replace replication in designing or re-designing reliable distributed storage systems. One promising alternative of replication is Erasure Coding (EC), which trades off extra computation for high reliability and availability at a prominently low storage overhead. Therefore, many existing distributed storage systems (e.g., HDFS 3.x, Ceph, QFS, Google Colossus, Facebook f4, and Baidu Atlas) have started to adopt EC to achieve storage-efficient fault tolerance. However, as EC introduces extra calculations into systems, there are several crucial challenges to think through for exploiting EC. Such as how to leverage heterogeneous EC-capable hardware (e.g., CPUs, General-Purpose Graphics Processing Units (GPGPUs), Field-Programmable Gate Arrays (FPGAs), and Smart Network Interface Cards (SmartNICs)) to accelerate EC computation and bring emergent devices and technologies into the pictures for designing high-performance erasure-coded distributed storage systems. In this dissertation, we propose Mint-EC, a high-performance EC framework to address the aforementioned research challenges. Mint-EC includes three major pillars: 1) a multi-rail EC library that enables upper-layer applications to leverage heterogeneous EC-capable hardware devices to perform EC operations simultaneously and introduces unified APIs to facilitate overlapping opportunities between computation and communication, 2) a set of coherent in-network EC primitives that can be easily integrated into existing state-of-the-art EC schemes and utilized in designing advanced EC schemes to fully leverage the advantages of the coherent in-network EC capabilities on (open full item for complete abstract)

Committee: Xiaoyi Lu (Advisor); Xiaodong Zhang (Committee Member); Christopher Stewart (Committee Member); Yang Wang (Committee Member) Subjects: Computer Engineering; Computer Science

Doctor of Philosophy, The Ohio State University, 2020, Computer Science and Engineering

Modern High-Performance Computing (HPC) systems are enabling scientists from different research domains such as astrophysics, climate simulations, computational fluid dynamics, drugs discovery, and others, to model and simulate computation-heavy problems at different scales. In recent years, the resurgence of Artificial Intelligence (AI), particularly Deep Learning (DL) algorithms, has been made possible by the evolution of these HPC systems. The diversity of applications ranging from traditional scientific computing to the training and inference of neural-networks are driving the evolution of processor and interconnect technologies as well as communication middlewares. Today's multi-petaflop HPC systems are powered by dense multi-/many-core architectures and this trend is expected to grow for next-generation systems. This rapid adoption of these high core-density architectures by the current- and next-generation HPC systems, driven by emerging application trends, are putting more emphasis on the middleware designers to optimize various communication primitives to meet the diverse needs of the applications. While these novelties in the processor architectures have led to increased on-chip parallelism, they come at the cost of rendering traditional designs, employed by the communication middlewares, to suffer from higher intra-node communication costs. Tackling the computation and communication challenges that accompany these dense multi-/manycores garner special design considerations. Scientific and AI applications that rely on such large-scale HPC systems to achieve higher performance and scalability often use Message Passing Interface (MPI), Partition Global Address Space (PGAS), or a hybrid of both as underlying communication substrate. These applications use various communication primitives (e.g., point-to-point, collectives, RMA) and often use custom data layouts (e.g., derived datatypes), spending a fair bit of time in communication an (open full item for complete abstract)

Committee: Dhabaleswar K. (DK) Panda (Advisor); Radu Teodorescu (Committee Member); Feng Qin (Committee Member); Hari Subramoni (Committee Member) Subjects: Computer Science

Doctor of Philosophy, The Ohio State University, 2019, Computer Science and Engineering

Sparse matrix/tensor operations have been a common computational motif in a wide spectrum of domains - numerical linear algebra, graph analytics, machine learning, health-care, etc. Sparse kernels play a key role in numerous machine learning algorithms and the rising popularity of this domain increases the significance of the primitives like SpMV (Sparse Matrix-Vector Multiplication), SDDMM (Sampled Dense-Dense Matrix Multiplication), MF/TF(Sparse Matrix/Tensor Factorization), etc. These primitives are data-parallel and highly suitable for GPU-like architectures that provide massive parallelism. Real-world matrices and tensors are large-scale and have millions of data points, which is sufficient to utilize all the cores of a GPU. Yet, a data-parallel algorithm can become the bottleneck of an application and perform way below than the upper bound of the roofline model. Some common reasons are frequent irregular global memory access, low data reuse, and imbalanced work distribution. However, efficient utilization of GPU memory hierarchy, reduced thread communication, increased data locality, and an even workload distribution can provide ample opportunities for significant performance improvement. The challenge lies in utilizing the techniques across applications and achieve an even performance in spite of the irregularity of the input matrices or tensors. In this work, we systematically identify the performance bottlenecks of the important sparse algorithms and provide optimized and high performing solutions. At the beginning of this dissertation, we explore the application of cost-effective ML techniques in solving the format selection and performance modeling problem in the SpMV domain. By identifying a small set of sparse matrix features to use in training the ML models, we are able to select the best storage format and predict the execution time of an SpMV kernel as well. Next, we optimize the SDDMM kernel, which is a key bottleneck in fa (open full item for complete abstract)

Committee: P. (Saday) Sadayappan (Advisor); Atanas Rountev (Committee Member); Radu Teodorescu (Committee Member) Subjects: Computer Science

Master of Science, Miami University, 2019, Computer Science and Software Engineering

Avian Influenza Viruses (AIV) are highly adaptive and mutate continuously throughout their life-cycle. Subtype H5N1, also known as Highly Pathogenic Asian Avian Influenza, is of particular interest due to its rapid spread from Asia to other countries. Constant mutations in the protein sequences of AIVs cause antigenic drift which leads to the spread of epidemics to livestock, causing billions of dollars in socio-economic losses each year. Consequently, containment of AIV epidemics is of vital importance. Computational approaches to epidemic forecasting, specifically phylodynamic simulations, enhance in vivo analysis by enabling analysis of ecological parameters, evolutionary traits, and the ability to predict antigenic shifts to assist vaccine design. This work introduces an improvement on existing phylodynamic simulations models, called the HASEQ model, by using actual Hemagglutinin (HA) protein sequences, simulating mutations through amino acid substitution models, and implementing an amino-acid level antigenic analysis algorithm to model natural selection pressure. In contrast to prior approaches that rely on abstract representations of virus strains and mutations, HASEQ manipulates and yields actual HA strains to allow for robust validation and direct application of results to inform epidemic containment efforts. The validity of the HASEQ model is assessed via comparisons to WHO Nomenclature refined to represent strains present in 3 high risk countries. The model is calibrated and validated using thousands of simulations with wide-ranging parameter settings requiring over 2,500 hours of computation time. Results show that the model improvements yield results with the expected evolutionary characteristics at the cost of increasing computational run-time costs 10-fold.

Committee: Dhananjai Rao (Advisor); Eric Rapos (Committee Member); Eric Bachmann (Committee Member) Subjects: Bioinformatics; Biology; Computer Science; Epidemiology

Master of Science in Computer Engineering, University of Dayton, 2019, Electrical and Computer Engineering

As aircraft turbine engine technologies have evolved, a need has emerged to move from legacy monolithic control systems to a distributed paradigm. This thesis is based upon research performed to develop a distributed control architecture that is secure and robust against extreme environmental conditions. Background, the proposed architecture, design of a network smart node, and experimental testing of a high-temperature microprocessor are presented.

Committee: Vamsy Chodavarapu Ph.D. (Committee Chair); Michael Wicks Ph.D. (Advisor); Guru Subramanyam Ph.D. (Committee Member) Subjects: Computer Engineering; Electrical Engineering

MDES, University of Cincinnati, 2018, Design, Architecture, Art and Planning: Design

With the rise of personal digital technology pervading human life, wellbeing has been negatively impacted by the excessive presence of technology in everyday life. In the midst of demonizing digital technology, Positive and Affective computing provide an alternative approach to design technology with the aim of improving well-being. This investigation focuses on stress care in women. The female body and mind stress response is different on a biological and psychological level from men. This thesis addresses stress to care for women only. From a biological perspective, the first part of this thesis reviews the stress phenomenon in the human body. To then delve in the world of personal digital technology by conducting a comprehensive study of existing technology for wellbeing with a particular focus on stress care. A critical analysis of current approaches to design technology is conducted to later suggest a holistic approach to stress by employing Positive and Affective computing principles. From a feminist standpoint, this thesis draws attention to the lack of personal technology designed based on female needs available nowadays and proposes a model to design technology that posits women as creators and researchers but also, in the other side of the spectrum, as the end-users of digital technology products that are particularly beneficial to women.

Committee: Heekyoung Jung Ph.D. (Committee Chair); Edson Roy Cabalfin Ph.D. (Committee Member); Samantha Krukowski Ph.D. (Committee Member) Subjects: Design

PhD, University of Cincinnati, 2018, Engineering and Applied Science: Computer Science and Engineering

In Parallel Discrete Event Simulation (PDES), the pending event set refers to the set of events available for execution. These pending events are aggressively scheduled for execution in a Time Warp synchronized parallel simulation without strict enforcement of the causal relationship between events. For most discrete event simulation models, event processing granularity is generally quite small. On many-core and multi-core platforms, this decrease in granularity aggravates contention for the shared data structures which store these pending events. As the number of cores increase, a key challenge lies in providing effective, contention-free event list management for scheduling events. Lock contention, sorting, and scheduling order are the prime contributors to contention for access to the pending events set. Possible solutions to this problem include atomic read-write operations, hardware transactional memory, or synchronization-friendly data structures. The focus is on choosing efficient data structures for the pending event set and optimization of scheduling techniques that can improve the performance of the Time Warp synchronized parallel simulation. The following design concepts for optimizing the pending event set are explored in this dissertation: 1. an exploration of a variety of different data structures that are commonly used in the management of pending event set. In addition, the management of the pending event set using a Ladder Queue data structure is explored. The Ladder Queue forms a self-adjusting hierarchically partitioned priority queue that makes it particularly attractive for managing the pending event set 2. the elimination of sorting within the Ladder Queue partitions. Events are then scheduled from the lowest partition without concerns for their time order and causal independence of these events is assumed 3. an atomic read-write access to the Ladder Queue partition that holds the smallest available events is explored 4. Objec (open full item for complete abstract)

Committee: Philip Wilsey Ph.D. (Committee Chair); Nael Abu-Ghazaleh Ph.D. (Committee Member); Fred Beyette Ph.D. (Committee Member); Ali Minai Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member) Subjects: Computer Engineering

Doctor of Philosophy, The Ohio State University, 2018, Computer Science and Engineering

Cloud Computing platforms (e.g, Amazon EC2 and Microsoft Azure) have been widely adopted by many users and organizations due to their high availability and scalable computing resources. By using virtualization technology, VM or container instances in a cloud can be constructed on bare-metal hosts for users to run their systems and applications whenever they need computational resources. This has significantly increased the flexibility of resource provisioning in clouds compared to the traditional resource management approaches. These days cloud computing has gained momentum in HPC communities, which brings us a broad challenge: how to design and build efficient HPC clouds with modern networking technologies and virtualization capabilities on heterogeneous HPC clusters? Through the convergence of HPC and cloud computing, the users can get all the desirable features such as ease of system management, fast deployment, and resource sharing. However, many HPC applications running on the cloud still suffer from fairly low performance, more specifically, the degraded I/O performance from the virtualized I/O devices. Recently, a hardware-based I/O virtualization standard called Single Root I/O Virtualization (SR-IOV) has been proposed to help solve the problem, which makes SR-IOV achieve near-native I/O performance. Whereas SR-IOV lacks locality-aware communication support, which makes the communications across the co-located VMs or containers not able to leverage the shared memory backed communication mechanisms. To deliver high performance to the end HPC applications in the HPC cloud, we present a high-performance locality-aware and NUMA-aware MPI library over SR-IOV enabled InfiniBand clusters, which is able to dynamically detect the locality information on VM, container or even nested cloud environment and coordinate the data movements appropriately. The proposed design improves the performance of NAS by up to 43% over the default SR-IOV based scheme across 32 VMs, whi (open full item for complete abstract)

Committee: Dhabaleswar K. Panda (Advisor); Yang Wang (Committee Member); Stewart Christopher (Committee Member); Sadayappan P (Committee Member); Xiaoyi Lu (Committee Member) Subjects: Computer Engineering; Computer Science