Master of Science in Engineering (MSEgr), Wright State University, 2006, Electrical Engineering

For the process of converting low-power digital signals into their high-power analog counterparts, the functions of digital-to-analog conversion (at low power) and analog power amplification are separately implemented. This thesis proposes a new “STAC-DAC” circuit topology which directly realizes high-power analog output from low-power digital input signals. The ability to achieve a “direct from digital” high-power analog output in a single high-efficient, low-distortion design has significant potential in audio reproduction, and flexible signal generation applications. In this thesis, the “STAC-DAC” is described and its implementation via MATLAB and LTSpice is discussed. The results of simulations are used to prove the concept of the design. The 16-bit design features a high-power output of 100 watts or more at an efficiency of 93%. The design is optimized to feature low total harmonic distortion (THD) of 0.055% for a 1 kHz signal at 100 watts into an 8 Ω load and low phase distortion of less than 10° for a 20 kHz signal and only 1° at 1 kHz. The “STAC-DAC” design is applicable to any design which requires a high-power analog output that is controlled by a logic level digital input. The results validated that the “STAC-DAC” can produce low-level THD figures over the audio frequency range. If very low THD figures are not necessary, high-power analog operation can be achieved into the hundreds of kilohertz while maintaining high efficiency. These results show that the power “STAC-DAC” is capable of simultaneously achieving the highly efficient circuitry associated with digital-to-analog converters with the low harmonic and phase distortion requirements associated with high fidelity analog audio amplifiers.

Committee: Marian Kazimierczuk (Advisor) Subjects:

Master of Science, University of Akron, 2013, Electrical Engineering

This work presents a low power, small size bio-signal amplifier with extended linear operation range. The proposed scheme consists of an open loop rail-to-rail differential amplifier in the first stage and a closed loop amplifier in the second-stage that minimizes the gain reduction with output voltage level variation. Furthermore, an additional gain control feature compensates the gain degradation as the amplifier output level moves toward the supply rails. Voltage buffers are used in the first and second stages in a way that enables using smaller sized feedback resistors in the second stage. The amplifier performance is relatively insensitive to feedback resistor mismatch. In addition to providing an extended linear operation range, this approach reduces the area and power which is required for portable medical devices. The proposed amplifier is implemented using CMOS 0.35 ¿¿m technology with 3.3 V supply. The measurement results show a constant gain of 46 dB with linear operation range from 0.3 V to 3.08 V. The total harmonic distortion (THD) is 0.04% with power consumption of 18.5 ¿¿W and a core area of 0.063 mm^2.

Committee: Kye-Shin Lee Dr. (Advisor); Robert Veillette Dr. (Committee Member); Joan Carletta Dr. (Committee Member) Subjects: Electrical Engineering