Doctor of Philosophy, The Ohio State University, 2013, Materials Science and Engineering

In the past twenty years, III-nitride devices have had an enormous impact on semiconductor-based technologies. This impact is seen in both optoelectronic and electronic devices. The aim of this dissertation is to take advantage of III-nitride nanowires grown by plasma-assisted molecular beam epitaxy to form heterostructures that are difficult or impossible to achieve in traditional, thin films. To do this, it is first necessary to establish the growth phase diagrams that correlate the characteristics of GaN nanowires to MBE growth conditions. By using the information in these growth maps we can control growth kinetics and the resulting nanowire structures by making strategic, timely changes to growth conditions. Using this control electronic and optoelectronic III-nitride nanowire devices are created. First, coaxially-oriented AlN/GaN nanowire resonant tunneling diodes are formed on Si substrates. Second, polarization-induced nanowire light emitting diodes (PINLEDs) are fabricated that exhibit electroluminescence at wavelengths from the deep UV into the visible. Because these PINLEDs utilize polarization doping, they can be formed with and without the use of dopants. Device and structural characterization are provided, including a detailed investigation of the mixed material polarity in these nanowires. Finally, the dissertation closes with a discussion of recent work and future ideas for optimizing the PINLED design.

Committee: Roberto Myers (Advisor); Siddharth Rajan (Committee Member); Tyler Grassman (Committee Member) Subjects: Materials Science

Doctor of Philosophy, The Ohio State University, 2012, Electrical and Computer Engineering

Handheld devices, such as cellphones, dominate consumer electronics market today and are foreseen to grow further in future years. One of the primary challenges with these devices is reducing the power consumption while keeping the operating frequencies high. Scaling of transistor dimensions has contributed to both increasing chip operating frequencies and greater functionality per unit area. However, as dimensions enter a few 10's of nanometer, leakage currents have also increased, escalating the overall power consumption. Scaling of supply voltage is a key to keep both dynamic and static power consumption low. Tunneling-based devices are investigated to address this challenge. Tunnel diodes in conjunction with conventional transistors can be used in novel circuit topologies to develop high speed circuits operating below 0.5V. However, large scale manufacture requires a Si-based device structure that can be fabricated with tools compatible with standard CMOS processing. In this dissertation, Si-based resonant interband tunnel diodes (RITD) are fabricated using chemical vapor deposition (CVD). High peak to valley current ratio's (PVCR) of 5.2 are obtained through optimization of the boron δ-doping with peak current densities of 20 A/cm2. This is the largest PVCR for silicon based tunnel diodes fabricated using CVD. Further, integration into a standard electronic design automation (EDA) tools is essential to enable development of very large scale integrated (VLSI) circuits. Tunnel diodes have been integrated into the Cadence EDA tool and a 32 x 32 bit tunneling SRAM (TSRAM) memory array has been designed with a standard 90 nm product development kit (PDK) obtained from MOSIS, for use as embedded memory. This provides a platform to compare TSRAM performance with the currently dominant SRAM and embedded DRAM technologies. Its performance and robustness to process variation is evaluated for a supply voltage of 0.5V. Read access times of 1 ns and write access times of (open full item for complete abstract)

Committee: Paul Berger (Advisor); Marvin White (Committee Member); Patrick Roblin (Committee Member) Subjects: Electrical Engineering