MS, University of Cincinnati, 2013, Engineering and Applied Science: Electrical Engineering

Power dissipation has now become the most critical design constraint. Up till now, in the design flow of any SoC, power estimation and analysis came into the picture only after the completion of RTL synthesis. However, design optimization for low power is most suitable before synthesis. Each decrease in process geometry makes dynamic power targets harder to achieve. Also, changes made later in the design for power optimization lead to costly re-spin. It is better to pin-point power related problems in the design as early as possible when they can still be fixed. It also reduces risk by ensuring that the design meets power goals before embarking on its implementation. A novel approach is presented in this thesis which introduces power analysis at the RTL stage itself using PSL assertions. This will enable the SoC designer to optimize the design from a low power perspective at a very early stage (RTL) in the design flow where the scope of modification is maximized and the cost minimized.

Committee: Carla Purdy Ph.D. (Committee Chair); Wen Ben Jone Ph.D. (Committee Member); Xuefu Zhou Ph.D. (Committee Member) Subjects: Electrical Engineering