Master of Science (M.S.), University of Dayton, 2015, Electrical Engineering

This Thesis describes a communication system to allow for the transmission of data between a host computer and a DE2-115 FPGA board over an Ethernet connection. This is achieved by using a socket between the host computer and a NIOS II embedded processor that accepts the data from the host computer and transfers it to the FPGA fabric. The host computer uses a C++ program to open a file and send the data over the socket to the NIOS II processor. The NIOS II acts as memory controller for the Synchronous Dynamic Random Access Memory (SDRAM) on the board with separate input and output data sections for the Hardware Description Language (HDL) processing module. A HDL module then processes the data and sends it back to the NIOS II to be returned to the host computer over the socket. The data transfer system is tested with three basic image processing functions performed on three sample images to verify its functionality. This data transfer system allows for easier testing of digital designs on the DE2-115 board by providing test data to the digital design in an efficient manner.

Committee: Eric Balster Ph.D. (Committee Chair); John Weber Ph.D. (Committee Member); Tarek Taha Ph.D. (Committee Member) Subjects: Electrical Engineering

Master of Science (M.S.), University of Dayton, 2012, Electrical Engineering

Image compression standards continually strive to to achieve higher compression ratios while maintaining image quality. In addition to these goals, new applications require expanded features and flexibility as compared to existing compression standards. JPEG2000 is the latest in the line of image compression standards, offering higher compression ratios than its predecessor JPEG while maintaining comparable image quality. In addition, JPEG2000 offers an extended range of features including bit-rate control, region of interest coding and file-stream scalability with respect to resolution, image quality, components and spatial region. However, these additional features come with associated costs, primarily in the form of computational complexity. Due to the increased computational costs, JPEG2000 has not achieved the same wide-spread usage as JPEG. However, there are a number of specialized applications such as medical imaging and wide-area surveillance which demand the extended features offered by JPEG2000. These applications generally deal with high resolution imagery, resulting in extremely long encoding times when using consumer off the shelf platforms. As a result, many hardware implementations of the most computationally complex portions of JPEG2000, namely Tier I encoding, have been proposed. This thesis proposes using an embedded soft-core processor on a Field Programmable Gate Array (FPGA) for JPEG2000 code stream organization, known as Tier II. The soft-core processor chosen, Altera's NIOS II core, is coupled with existing Discrete Wavelet Transform (DWT) and Tier I implementations on a single FPGA to realize a fully embedded JPEG2000 encoder. Results show the feasibility of using an embedded soft-core processor on a FPGA to perform Tier II processing for JPEG2000.

Committee: Eric Balster PhD (Committee Chair); John Weber PhD (Committee Member); Frank Scarpino PhD (Committee Member) Subjects: Computer Engineering; Electrical Engineering

MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering

Students with an interest in embedded systems come from a variety of backgrounds: EE, COMPE, CS, Telecommunications, etc. The students may be on-campus students or distance learning students. In particular, they have different levels of expertise in hardware and software and they will work or do research in a variety of settings, with many different system environments. For an embedded systems course to serve all the aforementioned groups, the course material has to follow an approach from hardware to software illustrating general concepts as well as practical experience. The course should be self-contained and flexible enough to support distance learning courses as well. However, there do not exist teaching materials at the appropriate levels and sufficiently detailed to properly train beginning students in the many areas they need to master. This thesis attempts to remedy that lack in the area of real time operating systems (RTOS). The proposed RTOS tutorials on an embedded, FPGA-based development platform will start with specifying the necessary hardware system then progress to the RTOS application. The necessary operating system (OS) and real time operating system (RTOS) concepts will be introduced to facilitate successful RTOS application development. The RTOS tutorials will be built upon the Altera Nios II soft-core processor and the Micrium MicroC/OS II RTOS utilizing RTOS concepts that can be applied to different RTOS's and embedded platforms.

Committee: Carla Purdy Ph.D. (Committee Chair); Yiming Hu Ph.D. (Committee Member); George Purdy Ph.D. (Committee Member) Subjects: Computer Engineering