Master of Sciences, Case Western Reserve University, 2022, EECS - Electrical Engineering

Frequency synthesizers play a crucial role in modern wireless communications as the local oscillator in a transceiver's upconverter and downconverter. One type of frequency synthesizer utilizes a phase-locked loop (PLL) to generate a frequency that is a multiple of a fixed reference. Integer-N PLLs are typically insufficient in modern wireless standards due to tight channel spacing putting a restrictive limit on reference frequency and bandwidth. Fractional-N PLLs, however, can precisely generate an output frequency that is a fractional multiple of the reference by toggling between division ratios. This thesis covers the design and simulation of a 1.2GHz low-power fractional-N PLL-based frequency synthesizer in 65nm CMOS. System-level and circuit-level design choices and simulations are shown, including a true single phase clock phase frequency detector, a charge pump, a 3rd order loop filter, a voltage-controlled oscillator, a toggleable frequency divider, and a 16-bit 2nd order delta sigma modulator.

Committee: Hossein Lavasani (Committee Chair); Christian Zorman (Committee Member); Pedram Mohseni (Committee Member) Subjects: Electrical Engineering

Master of Engineering, Case Western Reserve University, 2025, EMC - Aerospace Engineering

Analysis of three missions has been carried out with a set of three power and three propulsion systems to determine system synergy as well as to find an optimal system for each mission. The three missions are GTO to LLO, LMO, and Titan flyby. The three propulsion systems of analysis are Hall Effect Thrusters, Magnetoplasmadynamic Thrusters, and VASIMR Thrusters. The three power systems of analysis are Silicon photovoltaics, multi-junction photovoltaics, and nuclear reactors. The mission to Low Lunar Orbit has a maximum trip time of 8 weeks, and four systems are capable of achieving this result. Those systems are Hall-Nuclear, MPDNuclear, VASIMR-MJ, and VASIMR-Nuclear, the last of which achieves the target in just 26 days. The VASIMR-Nuclear system is also capable of bringing the most passengers with a total capacity of 255 people. The mission to LMO was limited to a maximum trip time of 9 months, and 1 system is capable of achieving this result. This system is again VASIMR-Nuclear, capable of bringing 31 people the LMO in 241 days, or about 8 months. The mission to Titan flyby using the VASIMR-Nuclear system is capable of bringing 54500 kg of dry mass to Titan flyby at 1000 km at 3.13 km/s relative to the planet.

Committee: Paul Barnhart (Advisor); Majid Rashidi (Committee Member); Richard Bachmann (Committee Member) Subjects: Aerospace Engineering

Doctor of Philosophy, Case Western Reserve University, 2024, EECS - Electrical Engineering

5G promises higher speed for data communication when Internet-of-Things (IoT) makes enormous number of devices connected to each other. Preserving the security and trust in such systems are one of the critical. To create secure and trustworthy system while preserving the low power nature of such circuits, this work introduces a novel concept: embedded analog Physically Unclonable Functions (PUFs). Embedded analog PUFs provide enable lower power consumption than conventional hardware security methods because they are implemented in target circuits such as Voltage Controlled Oscillator (VCO) or Low Noise Amplifier (LNA). Also, the proposed approach allows for using performance parameters of the target circuits to develop required unique Challenge-Response Pair (CRP) mechanisms instead of bit streams of conventional PUF designs. In this work, power hungry parts of a radio frequency front-end (RF-FE), i.e. VCO and LNA, are targeted. Prototype low power 28 GHz trusted VCO and trusted LNA are developed in 65-nm standard CMOS and 22-nm FDSOI processes. Embedded analog PUF in VCO and LNA allows adjusting the DC (e.g. current consumption) and AC (e.g. frequency and noise figure (NF)) properties of the VCO and LNA to authenticate the designs while providing competitive performance with the VCO achieving figure of merit (FoM) of 195.2 dBc/Hz @1 MHz offset, and LNA showing NF ~ 3.7 dB @ 28 GHz.

Committee: Hossein Miri Lavasani (Committee Chair); Francis Merat (Committee Member); David Kazdan (Committee Member); An Wang (Committee Member); Steve Majerus (Committee Member) Subjects: Computer Engineering; Electrical Engineering; Electromagnetics

Master of Science in Engineering, Youngstown State University, 2022, Department of Electrical and Computer Engineering

Bluetooth Low Energy (BLE) has emerged as one of the main wireless technologies used in low-power electronics, such as wearables, beacons, and devices for the Internet of Things (IoT). BLE's energy efficiency characteristics and ease of use interface are essential features for the design of ultralow-power devices. The integration of BLE with various sensors is certainly the main aspect for the development of efficient solutions, and monitoring the power consumption of the device in all the cycles of operation is important for decisions such as advertising interval, sensor routine and data transmission. Recent work of BLE power analysis focuses on the theoretical aspects of the advertising and scanning cycles, with most results being presented in the forms of mathematical models and computer software simulations. Such models and simulations are particularly important for the understanding of the technology. However, many times they leave real applications out of scope. This thesis covers the implementation of a multi-sensor Bluetooth Low Energy system, and the study of the communication protocol regarding its power consumption and RF performance. The implementation consists of a battery powered custom Printed Circuit Board (PCB) featuring the Texas Instruments CC1352P7 as the main SoC and three different sensors capable of measuring 6 different parameters. The sensors are the BME688 from Bosch, and the ADXL343 and AD5941 from Analog Devices. The characterization process was performed using Keysight EXR Oscilloscope and 208A Spectrum Analyzer. The proposed design has dimensions of 28 mm × 35 mm. The current consumption of the implemented design with one sensor in operation is 4.1mA and 7.1mA, and 6.9 mA combined.

Committee: Frank Li PhD (Advisor); Pedro Cortes PhD (Committee Member); Vamsi Borra PhD (Committee Member) Subjects: Computer Engineering; Electrical Engineering

Doctor of Philosophy (PhD), Wright State University, 2022, Electrical Engineering

Binary multipliers are ubiquitous in digital hardware. Digital multipliers along with the adders play a major role in computing, communicating, and controlling devices. Multipliers are used majorly in the areas of digital signal and image processing, central processing unit (CPU) of the computers, high-performance and parallel scientific computing, machine learning, physical layer design of the communication equipment, etc. The predominant presence and increasing demand for low-power, low-cost, and high-performance digital hardware led to this work of developing optimized multiplier designs. Two optimized designs are proposed in this work. One is an optimized 8 x 8 Booth multiplier architecture which is implemented using 32nm CMOS technology. Synthesis (pre-layout) and post-layout results show that the delay is reduced by 24.7% and 25.6% respectively, the area is reduced by 5.5% and 15% respectively, the power consumption is reduced by 21.5% and 26.6% respectively, and the area-delay-product is reduced by 28.8% and 36.8% respectively when compared to the performance results obtained for the state-of-the-art 8 x 8 Booth multiplier designed using 32nm CMOS technology with 1.05 V supply voltage at 500 MHz input frequency. Another is a novel radix-8 structure with 3-bit grouping to reduce the number of partial products along with the effective partial product reduction schemes for 8 x 8, 16 x 16, 32 x 32, and 64 x 64 signed multipliers. Comparing the performance results of the (synthesized, post-layout) designs of sizes 32 x 32, and 64 x 64 based on the simple novel radix-8 structure with the estimated performance measurements for the optimized Booth multiplier design presented in this work, reduction in delay by (2.64%, 0.47%) and (2.74%, 18.04%) respectively, and reduction in area-delay-product by (12.12%, -5.17%) and (17.82%, 12.91%) respectively can be observed. With the use of the higher radix structure, delay, area, and power consumption can be further reduced. (open full item for complete abstract)

Committee: Saiyu Ren Ph.D. (Advisor); Raymond E. Siferd Ph.D. (Committee Member); Henry Chen Ph.D. (Committee Member); Marian K. Kazimierczuk Ph.D. (Committee Member); Yan Zhuang Ph..D. (Committee Member); Michael Saville Ph.D., P.E. (Other); Barry Milligan Ph.D. (Other) Subjects: Computer Engineering; Electrical Engineering

Master of Science in Cyber Security (M.S.C.S.), Wright State University, 2022, Computer Science

The current Routing Protocol for Low Power and Lossy Networks (RPL) standard provides three security modes Unsecured Mode (UM), Preinstalled Secure Mode (PSM), and Authenticated Secure Mode (ASM). The PSM and ASM are designed to prevent external routing attacks and specific replay attacks through an optional replay protection mechanism. RPL's PSM mode does not support key replacement when a malicious party obtains the key via differential cryptanalysis since it considers the key to be provided to nodes during the configuration of the network. This thesis presents an approach to implementing a secure authenticated key exchange mechanism for RPL, which ensures the integrity and authentication of the received key while providing tamper-proof data communication for IoTs in insecure circumstances. Moreover, the proposed approach allows the key to be updated regularly, preventing an attacker from obtaining the key through differential cryptanalysis. However, it is observed that the proposed solution imposes an increase in the cost of communication, computation, power consumption, and memory usage for the network nodes.

Committee: Bin Wang Ph.D. (Advisor); Zhiqiang Wu Ph.D. (Committee Member); Meilin Liu Ph.D. (Committee Member) Subjects: Computer Science

Bachelor of Science, Walsh University, 2022, Honors

Currently the information available on how to properly train youth athletes is limited due to the lack of studies performed on this population. It is widely understood that youth athletes should be trained in some manner but exactly how they might be trained for maximum effectiveness is still unclear. To better understand how to train youth athletes this study looks at 16 male athletes between the ages of 14 and 18 years old who participate in at least one sport and have had at least a youth of strength training experience. The study aims to determine how relative strength levels in the squat and deadlift effect the performance of five athletic indicators, the max hang high pull, 40-yard dash, 10-yard dash, max broad jump, and 3-cone drill. These were the chosen indicators because each movement demonstrates an athletes' speed, agility, and power production all of which are essential markers of athletic success. Each athlete performed a max squat and deadlift to determine their relative strength levels where the highest eight scores of each lift were placed in a high strength group and the lowest eight were placed in the low strength groups. Correlational analyses were run to determine if there were any correlations between strength levels and performance each of the athletic indicators. One-way ANOVA tests were run between the high and low strength squat and deadlift groups respectively to determine if there was a significant difference between the high and low strength groups of each lift. There was a significant correlation between relative squat strength and each of the five indicators at the .05 level, there was also a significant correlation between relative deadlift strength and each of the five indicators at the .05 level. The one-way ANOVA tests revealed there was a significant difference (p ≤ .05) between the high and low relative deadlift strength groups in each of the five indicators while there was also a significant difference between the high and low r (open full item for complete abstract)

Committee: Kelton Mehls (Advisor) Subjects: Health; Health Sciences; Physical Education; Sports Medicine

Doctor of Philosophy (Ph.D.), University of Dayton, 2021, Electrical Engineering

The demand for autonomous systems is increasing in multiple domains, including mobile systems (UAVs, cars, and robots) and planning systems, as it improves the performance of the systems beyond human capabilities. In autonomous systems, agents mine a massively large knowledge database to make intelligent and optimal decisions in run-time. Knowledge mining and decision-making are cast as constraint satisfaction problems (CSP), where solutions are generated by satisfying a number of constraints from the domain. CSPs have become a point of interest because of their affiliation with both artificial intelligence and operations research. From resource allocation and automated decision-making to gaming, constraint satisfaction problems are widely noticeable. An autonomous system achieves its autonomy by solving these problems using CSP solving approaches, including Boolean satisfiability, satisfiability modulo theories, answer set programming. Autonomy is the degree of acquired autonomous capability. Within the Air Force, autonomy is defined as the ability to select the required course of action (COA) to achieve higher objectives. The Cognitively Enhanced Complex Event Processing (CECEP) framework being developed at the US Air Force is an autonomous decision support tool that enables enhanced agent-based decision making. CECEP enables the autonomous system to process complex real-world events and select the required course of action to achieve optimal results. CECEP is capable of representing and processing declarative, procedural, and domain-specific knowledge to deal with all forms of real-world events. CECEP also incorporates several task independent knowledge processing frameworks to perform as a generic problem-solving framework. CECEP's problem-solving capability makes it a universal complex event processing framework that can be utilized in both military and civilian domains. CECEP captures its domain knowledge in a cognitive domain ontology (CDO), storing it (open full item for complete abstract)

Committee: Tarek Taha (Committee Chair) Subjects: Electrical Engineering

Master of Science (MS), Ohio University, 2021, Mechanical Engineering (Engineering and Technology)

Potential energy savings for small unmanned multirotor copters inside Ground Effects (GE) could be used to increase flight time or mission payload. Operating Inside Ground Effects (IGE) presents non-linear thrust responses potentially introducing instabilities requiring more advanced control than currently present on small autopilot systems. While maximum energy savings are found for rotorcraft hover flight IGE, low altitude forward flight has been shown to offer partial energy saving for small forward velocities compared to hover. The aim of this research was to explore multirotor copter forward flight IGE using an aerodynamics model, such as Blade Element Momentum Theory (BEMT), and quadcopter simulation flights. An existing BEMT method designed to include GE was further modified to consider the impacts forward flight on rotor thrust output for sUAS sized propellers. Thrust results were then adapted to the rotor dynamics of the quadcopter model to simulate low altitude flight of a multirotor sUAS. Non-linear dynamic inversion was used to stabilize the rotorcraft dynamics IGE and maintain specific Height Ratios (HR) during forward flight. GE thrust boosts were compensated for using a GE strength determination method which predicted the rotor GE response by monitoring individual rotor altitudes. Rotor power data collected from quadcopter simulation flights both OGE and IGE were used to identify flight conditions with decreased rotor power and measure the control effort needed multirotor flight IGE. Simulation results found average rotor power to decrease with decreasing HR and forward flight velocity. Increasing forward flight velocity was found to decrease the range of HR where GE energy savings were still present. Flight conditions with decreased power requirements were identified and grouped within an increased rotor efficiency region ranging from HRs of 0.5 to 2 and a forward flight ratios of 0 to 1.5. The increased efficiency region included a range of flight c (open full item for complete abstract)

Committee: Jay Wilhelm (Advisor); Sergio Ulloa (Committee Member); Douglas Lawrence (Committee Member); Robert Williams (Committee Member) Subjects: Aerospace Engineering; Energy; Engineering

Master of Sciences (Engineering), Case Western Reserve University, 2021, EECS - Electrical Engineering

This thesis presents an innovative cross-coupled differential drive rectifier for ultra-low power RF energy harvesting applications. Designed in a standard 65-nm complementary metal oxide semiconductor (CMOS) process, it employs dynamic threshold compensation and forward body biasing techniques to compensate for the threshold of MOS devices. A simple off-chip differential matching network is used to interface with the antenna. Post-layout simulations show that the proposed single-stage rectifier achieves a power conversion efficiency (PCE) > 10% and produces output voltage > 160 mV (at 300 kΩ load) when receiving a 2.4 GHz signal with average power of -30dBm. The measurement results show that the proposed rectifier reaches 10% PCE when receiving a 2.4 GHz signal with average power of -27dBm (at 100kΩ load). Compared to the state-of-the-art, the result shows favorable performance for low input powers (<-27 dBm) despite operating at higher frequency.

Committee: Hossein Lavasani (Advisor); Francis Merat (Committee Member); Christian Zorman (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 2021, Electrical and Computer Engineering

In applications such as networked monitoring and control systems, wireless sensor networks, and autonomous vehicles, it is crucial for the destination node to receive timely status updates so that it can make accurate decisions. For example, a moving car with a speed of 65 mph will traverse almost 29 meters in 1 second, and hence, stale information (regarding the location of surrounding vehicles, velocities, etc.) has a dramatic serious impact on this situation. Age of information (AoI), or simply age, has been used to measure the freshness of status updates. More specifically, AoI is the age of the freshest update at the destination, i.e., it is the time elapsed since the freshest received update was generated. It should be noted that optimizing traditional network performance metrics, such as throughput or delay, does not attain the goal of timely updating. For instance, it is well known that AoI could become very large when the offered load is high or low. In other words, AoI captures the information lag at the destination, and is hence more apt for achieving the goal of timely updates. In this thesis, we leverage rigorous theory to develop low-complexity scheduling algorithms that are apt for a wide range of information update systems. In particular, we consider the following systems: -Information update systems with stochastic packet arrivals: We consider single and multihop networks with stochastic arrivals, where our goal is to answer the following fundamental questions: (i) Which queueing discipline can minimize the age? And (ii) under what conditions is the minimum age achievable? Towards this goal, we design low-complexity scheduling policies to achieve (near) age-optimality in single and multihop networks with single source. The achieved results that we present here hold under quite general conditions, including (i) arbitrary packet generation and arrival processes, (ii) for minimizing both the age processes in stochastic ordering and any non-d (open full item for complete abstract)

Committee: Ness Shroff (Advisor); Yin Sun (Other); Atilla Eryilmaz (Committee Member); Abhishek Gupta (Committee Member); Qin Ma (Committee Member) Subjects: Communication; Computer Engineering; Electrical Engineering

Master of Sciences, Case Western Reserve University, 2019, EECS - Electrical Engineering

New research tools are essential to understanding neural control of the lower urinary tract (LUT) and could enable new treatments or neuroprosthesis to eliminate incontinence. Modern technologies enable real-time, catheter-free monitoring of bladder pressure, however variations in physiology among animals and people complicate interpretation of pressure data without bladder volume information. To date, no available technology achieves catheter-free, chronic monitoring of bladder volume. This thesis describes the design of a fully-wireless device for conductivity-corrected conductance measurements of fluid volume in a catheter-free system. The device consists of two electrodes, one sensing anode, and a microcontroller, and is small enough for surgical implantation within the bladder lumen. In-vitro benchtop testing demonstrated fluid volume prediction with <5mL mean error below 40mL and a worst-case mean error of 13mL near full-scale volume. These results indicate that conductance-based volume sensing of the urinary bladder is a feasible method for real-time catheter-free urine volume measurement.

Committee: Christian Zorman Dr. (Committee Chair); Margot Damaser Dr. (Committee Member); Soumyajit Mandal Dr. (Committee Member); Steve Majerus Dr. (Committee Member) Subjects: Biomedical Engineering; Electrical Engineering

Doctor of Philosophy (PhD), Wright State University, 2018, Electrical Engineering

The development trend of power converters motivates the pursuit with high density, high efficiency, and low cost. Increasing the frequency can improve the power density and lead to small passive elements and a fast dynamic response. Each one of these power converters must be driven by a gate-drive circuit to operate efficiently. Conventional gate-drivers are used up to frequencies of about 5 MHz and suffer from switching losses. Therefore, the development of switch-mode power supplies (SMPS) operating at high frequencies requires high-speed gate drivers. The presented research in this dissertation focuses on analysis, design, and development of new types of resonant gate-drive circuits to drive power transistors at high frequencies. Three proposed topologies are presented in this dissertation. Two topologies are single-switch ZVS gate-drive circuits. The attractive features of the two circuits are : (a) suitable to drive a low-side power transistor, (b) capable of operating at high frequencies with quick turn-on and turn-off transitions, (c) low power loss due to zero-voltage switching in the driving switch, (d) a significant increase in gate-source voltage of the driven switch with respect to the input voltage, (e) small energy storage components, and (f) designed to operate at switching frequency 20 MHz and a supply voltage of 4 V. The third presented topology is a class-D resonant gate-drive circuit. A series resonant circuit is formed by the resonant inductor and the input capacitance of the MOSFET to achieve the charge and discharge process of the transistor input capacitance. The proposed circuit can be used as a gate-drive circuit to drive low-side or high-side power switches operating at 6.78 MHz. In each above topology, detailed steady-state operation and derived expressions for the steady-state waveforms are presented. The analysis includes predicted power loss expressions in circuit components to estimate the overall losses in the gate-drive cir (open full item for complete abstract)

Committee: Marian K. Kazimierczuk Ph.D. (Advisor); Ray Siferd Ph.D. (Committee Member); Henry Chen Ph.D. (Committee Member); Saiyu Ren Ph.D. (Committee Member); Yan Zhuang Ph.D. (Committee Member) Subjects: Electrical Engineering; Engineering

Doctor of Philosophy, The Ohio State University, 2018, Electrical and Computer Engineering

Microcontroller Units (MCUs) are central and essential to many consumer electronic and industrial applications, including communication systems, automotive, and Internet of Things (IoT). Since, these MCUs can be used in various applications with different operating conditions, designing the internal power supply of such MCUs is quite challenging. For example, in some applications the MCUs could be powered from a Li-ion battery while in other application it could be powered from on-board regulator, or even an AC-to-DC adapter. This indeed requires the internal power supply of such MCUs to handle a very wide range of input voltages. In addition, these MCUs typically contains analog and digital circuits that operates from different supply levels. As a result, the internal power supply of the MCU has also to support a wide range of output voltage instead of designing separate power supply for each block which requires additional design and layout efforts. Moreover, depending on the performance requirements of the MCU or the mode of operation, the current consumption can vary very widely. It can be as high as 150-300 mA in active and high performance mode or it can be as low as 10-200 µA in sleep or idle mode. Consequently, the internal power supply of the MCU has to support a wide range of load currents. It is important to mention that since MCUs usually stay more than 50% of their time in sleep mode, the efficiency of their internal power has to be high not only in active mode (heavy load condition), but also in sleep mode (ultra-light load condition). Furthermore, each application puts different limitations and constrains on the passives (i.e. inductors or capacitors) used with the MCU. This includes different size and cost which exaggerate the constrains of the MCU's internal power supply which has to support a very wide range of passive components as well. Most importantly, since some low-noise MCUs usually contain noise sensitive IPs such as PLLs, Oscillators, and (open full item for complete abstract)

Committee: Ayman Fayed (Advisor); Patrick Roblin (Committee Member); Steven Bibyk (Committee Member) Subjects: Electrical Engineering

MS, University of Cincinnati, 2018, Engineering and Applied Science: Electrical Engineering

From a digital world where we make phones and twitter talk to each other, we are moving towards building a network where everyday objects communicate and share data among themselves. This platform known as Internet of Things (IoT) is a fast growing technology today where devices are connected via internet. In the next few years, the studies anticipate that billions of devices will be connected through internet and we will be heavily dependent on IoTs which will serve as the backbone of almost every sector[31]. Producing secure connections and secure devices is the need of the hour, and most of the devices as part of this connection are small-sized devices with low computational powers, while carrying private and sensitive information. Implementing low-level techniques to provide security such as WDDL[58], SDMLp[44] can be very expensive and affect its range of usage. The key objective of the thesis is to propose a Secure design methodology for such small devices which are used in today's high connectivity networks. This dissertation focuses on producing secure designs for small-to-medium sized Finite State Machines and the scope of the work is within the analysis of Power based side-channel attacks. The proposed algorithm for FSM state assignment, removes the reliance of its power consumption from the data carried within the FSM. The designer will be able to design the FSM with required security level at the cost of area. The thesis further discusses generation of state encodings for Low-power design without compromising on security. All the experiments have been performed on BenGen [27] and MCNC benchmarks [63] and the merit of the proposed algorithm has been proved.

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Wen-Ben Jone Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member) Subjects: Engineering

Master of Science in Engineering, University of Akron, 2018, Electrical Engineering

This work presents a successive-approximation-register (SAR) analog-to-digital converter (ADC) using a single-capacitor-pulse-width-to-analog converter-based digital-to-analog (DAC). In the proposed SAR ADC, the single-capacitor DAC is realized by partially charging or discharging the sampling capacitor with a DC reference current. The charge and discharge time is determined by the pulse width of the control signal. As a result, a SAR ADC can be realized by using a single capacitor, a current source, a current mirror, a comparator, and control logic; the result is a significant reduction in the circuit area and a simplified switch control scheme, compared to conventional SAR ADCs using capacitor DACs. A 6-bit 500kS/s SAR ADC is designed using CMOS 0.35µm technology, and the operation is verified through circuit level simulations. The effect of non-idealities including capacitor error, comparator offset, and current mismatch are analyzed, where ADC INL and DNL with each error are obtained. The power consumption of the ADC core was 22.6µw, which is lower than other designs. Aside from the low power consumption, with the single capacitor switching technique, the chip size is significantly reduced. The chip size of the proposed SAR ADC is around 0.01mm2, which is 60% to 80% smaller than other recent SAR ADC architectures.

Committee: Kye-Shin Lee (Advisor); Arjuna Madanayake (Committee Member); Seungdeog Cho (Committee Member) Subjects: Electrical Engineering

Master of Science in Electrical Engineering (MSEE), Wright State University, 2017, Electrical Engineering

The double-balanced Gilbert mixer is widely used in RF receivers. In general, it is desirable to design a wide tuning frequency Gilbert mixer for low power, high conversion gain, low noise figure, and good linearity, but they are not easy to attain simultaneously. Therefore, trade-offs always exist by tuning design parameters. To observe the trade-off relationship between each tunable parameter and to make a mixer achieve specified requirements easily (i.e., tuning frequency range, bandwidth, and power), an automated design synthesis and verification approach for Gilbert mixer is proposed. A wide tuning CMOS Gilbert mixer design synthesis while keeping the local oscillator frequency of 2 GHz is presented as an example. Designed in 180 nanometer CMOS process, the tunable Gilbert mixer achieves a tuning frequency span of 2 GHz (1.1 - 3.1 GHz), a controllable bandwidth of ~50 MHz, a high conversion gain (0.5 – 6.4 dB), a low noise figure (6.81 – 8.36 dB), and a power of 9 mW.

Committee: Henry Chen Ph.D. (Advisor); Yan Zhuang Ph.D. (Committee Member); Jiafeng Xie Ph.D. (Committee Member) Subjects: Electrical Engineering; Engineering

Doctor of Philosophy, The Ohio State University, 2017, Electrical and Computer Engineering

Synchronization plays an important and fundamental role as the timing basis in digital, analog, and RF integrated circuits (ICs), where Phase-Locked Loops (PLLs) find their versatile applications. The noise sources in a traditional PLL are mainly divided into two groups: noise before the low-pass loop filter such as the noise in the reference signal, Frequency Divider (FD), Phase Frequency Detector/Charge Pump (PFD/CP); and noise after the filter such as the Voltage Controlled Oscillator (VCO) noise and the loop filter noise. The output phase noise of the PLL is the combined contribution from these two equally important in-band and out-band noise sources. This research studies the effect of the synchronization in the PLL on the decoupling of the 3dB bandwidths for different noise sources to achieve an optimum phase noise and improved locking behavior with an attenuated reference signal injection (RI) into a ring-type delay-line Voltage Controlled Synchronous Oscillator (VCSO). This dissertation begins with the development of a generalized phase model for both LC-type and ring-type VCSOs. Next, the relationship between the device baseband noise (flicker and thermal noise) and a ring-type oscillator's phase noise is derived. In addition, noise shaping functions are introduced to describe signal injection into the VCSO to achieve suppression of the oscillator in-band phase noise. Then, the transient and steady-state behavior of a Charge-Pump PLL-RI are explained with nonlinear differential equations and the phase-plane method. The nonlinear phase equation is linearized for the small-signal condition and the s-domain noise transfer functions as well as noise bandwidths are derived for different noise sources in the major components of the PLL-RI. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. The analysis is verified by the SPICE simulation and experimental results from a Cha (open full item for complete abstract)

Committee: Marvin White (Advisor); Waleed Khalil (Committee Member); Steven Bibyk (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 2017, Computer Science and Engineering

Non-volatile memories such as Spin-Transfer Torque Random Access Memory (STT-RAM), Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), etc. are emerging as promising alternatives to DRAM and SRAM. These new memory technologies have many exciting characteristics such as non-volatility, high density, and near-zero leakage power. These features make them very good candidates for future processor designs in the power-hungry big data era. STT-RAM, a new generation of Magnetoresistive RAM, in particular is an attractive class of non-volatile memory because it has infinite write endurance, good compatibility with CMOS technology, fast read speed, and low read energy. With its good read performance and high endurance, it is feasible to replace SRAM structures on processor chips with STT-RAM. However, a significant drawback of STT-RAM is its higher write latency and energy compared to SRAM. This dissertation first presents several approaches to use STT-RAM for future low-power processor designs across two different computing environments (high voltage and low voltage). Overall our target is to take advantage of the benefits of STT-RAM over SRAM to save power and at the same time try the best to accommodate STT-RAM's write drawbacks with novel solutions. In high voltage computing environment, we present a low-power microprocessor framework -- NVSleep, that leverages STT-RAM to implement rapid checkpoint/wakeup of idle cores to save power. In low voltage computing environment, we propose an architecture - Respin, that consolidates the private caches of near-threshold cores into unified L1 instruction/data caches that use STT-RAM to save leakage power and improve performance. On top of this shared L1 cache design, we further propose a novel hardware virtualization core management mechanism to increase resource efficiency and save energy. Although the non-volatility feature of non-volatile memories can be leveraged to build power-efficient designs, it also brin (open full item for complete abstract)

Committee: Radu Teodorescu (Advisor); Feng Qin (Committee Member); Christopher Stewart (Committee Member); Yinqian Zhang (Committee Member) Subjects: Computer Engineering; Computer Science

Doctor of Philosophy (PhD), Wright State University, 2016, Engineering PhD

Today many consumer, industrial, and military electronic systems are digital in nature and are utilized for multiple applications. Many of these systems were designed to be portable and generally have limited capabilities because of size, weight, and power requirements. The last several decades have seen the push for more power efficient electronics. Thus, researchers and scientists investigated advanced process technologies and more power efficient circuit implementations. This research is concerned with classes of applications intended to operate over long periods of time with a low duty cycle, but are subject to bursts of information, requiring high processing capabilities. Specifically, this research focused on the development of an adaptive power digital interface suitable for remote sensor applications. These applications generally are equipped with an analog sensor that must be converted into a digital format for further processing. An analog-to-digital interface architecture with support for dynamically switching subsequent processing circuitry between performance, low power, and subthreshold modes was developed. This dissertation presents: 1. An understanding of CMOS operation across dynamic power modes is described. The intended applications require sensor systems to operate for extended periods of time with very low power consumption. It is feasible to operate such circuits in the subthreshold region, but certain tradeoffs are required to allow operation in the superthreshold region for performance. This work investigated potential tradeoffs to facilitate the development of supporting control circuitry. 2. Development of the Current Monitoring and Drive Compensation (CMDC) concept was undertaken as part of this work. CMDC allows the circuitry (i.e. processing, logic, storage) to be dynamically switched between performance and power modes. SPICE level simulations have shown that the architecture is feasible and can suppor (open full item for complete abstract)

Committee: Marian Kazimierczuk Ph.D. (Advisor); Henry Chen Ph.D. (Committee Member); Gregory Kozlowski Ph.D. (Committee Member); Ronald Coutu Ph.D. (Committee Member); Brad Bryant Ph.D. (Committee Member) Subjects: Electrical Engineering; Energy; Remote Sensing; Systems Design