MS, University of Cincinnati, 2022, Engineering and Applied Science: Electrical Engineering

To reduce Integrated Circuit (IC) manufacturing costs, many design houses prefer outsourcing the fabrication process to third party foundries. However, this may lead to IC designs being modified, counterfeited, and stolen by attackers. To mitigate the threats to ICs, logic encryption methods have been proposed. Logic Encryption is a hardware security enhancement technique in which logic gates driven by key inputs are added to the design. It requires the correct key input, known only to the designer, to be applied to the circuit to produce the correct output behavior. Aiming to maximise the security of a design, the logic encryption techniques often introduce the PPA (power, performance, area) overhead. Constraint Driven Logic Encryption (CDLE) is a method that considers PPA impact while encrypting the design. CDLE uses logic synthesis, physical synthesis and circuit simulation tools at every stage for PPA estimation which leads to prohibitively long time for encrypting large designs. This thesis research applies neural networks to predict the encryption scheme and the optimal key size range that offers the maximum security to a given logic design within seconds. Since neural networks predict the outputs more accurately when compared to other classifiers, a neural network trained using the circuit information and PPA overhead can be used to determine the encryption scheme and key size range that satisfies the security and cost constraints. The effectiveness of the proposed method is validated using designs from the existing benchmark suites such as ISCAS '85, ISCAS '89, and ITC '99. This thesis also presents a synthetic benchmark generator that generates SAT [5] resilient designs of various sizes and uses them to train and validate the neural networks.

Committee: Ranganadha Vemuri Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member) Subjects: Electrical Engineering

MS, University of Cincinnati, 2019, Engineering and Applied Science: Computer Engineering

With the advent of semi conductor design industry becoming fab-less to reduce the cost incurred on maintaining the fabrication units due to the advancements in the transistor node, the IC designs are outsourced for fabrication. Miscreants in the fabri- cation industry have the potential of misusing the Intellectual Property(IP) by reverse engineering the IC and over producing the design to sell them in the black market. Hence securing the IPs has become essential. Many techniques like Logic Encryption, Split Manufacturing and Camouflaging have been developed to thwart such attacks by hiding the functionality of the circuit from the attacker. Many logic encryption techniques for combinational circuits lock the original circuit with a key scheme to prevent the circuit from working as required until the correct key value is applied. Recently, a Boolean satisfiability based attack technique was pro- posed in [1] which was able to successfully decrypt and find the correct key scheme for many logically encrypted circuits within 10 hours. Subsequently, defense methods that are resilient to the SAT attack such as SARLOCK[2], Anti-SAT[3], TTLOCK[4], etc. were proposed. Sequential logic encrypted circuits have shown to be susceptible to the sequential-SAT attack [5], and the sequential SAT attack with incremental bounded- model-checking (BMC) [6]. In this thesis we present a novel technique to encrypt a sequential circuit which is SAT attack resilient. The techniques proposed in this thesis work are: • Deep State Encryption: In this technique, a sequential circuit is encrypted by inverting the values of the primary outputs based on the occurrence of a chosen deep state in the design. • Reduced Overhead Deep State Encryption: A modification to the Deep State Encryption technique that aims at reducing the area overhead introduced by the encryption scheme is proposed. • SAT Resilient Reduced Overhead Deep State Encryption: A more secure approach which corrupts inter (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Wen-Ben Jone Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member) Subjects: Computer Engineering

PhD, University of Cincinnati, 2024, Engineering and Applied Science: Electrical Engineering

In the semiconductor industry, protecting Integrated Circuits (IC) throughout the IC supply chain has become a major concern. With the globalization of the design process, the increasing cost of fabrication, and the complex manufacturing process of ICs, Hardware security has become a prominent issue. Especially, the increasing cost of IC fabrication has forced design houses to depend on potentially untrusted foundries to fabricate their ICs. At every step of the IC supply chain, ICs have become vulnerable to several potential attacks, including reverse engineering, overproduction, counterfeiting, trojan insertion, and IP theft. Design-for-trust schemes have emerged in recent years to overcome these threats. In-depth research has been done on logic encryption, split manufacturing, and layout camouflaging to safeguard ICs against attacks at various stages of the supply chain. Among the most promising schemes are logic encryption and layout camouflaging, which can thwart potential attacks at multiple supply chain stages. To safeguard ICs at every stage of the supply chain, including the foundry, the testing facility, and the end user, this research aims to create new logic locking strategies. We suggest creating a novel “SRTLock” two-tier logic encryption technique to protect the IC from sensitivity analysis attacks. In order to safeguard ICs at various points along the IC supply chain, we also proposed the “ISPLock” hybrid internal state locking method. In order to make sure that the IC cannot be used without the proper key, this technique also offers a high average output corruption rate (OCR) for the protected circuit. To increase the overall security of ICs, logic locking and camouflaging are both used together. Additionally, a “Hybrid Shielding” technique using polymorphic gates has been developed to guarantee security at every stage of the IC supply chain. It uses dynamic camouflaging and logic loc (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Wen-Ben Jone Ph.D. (Committee Member); Sumeet Chaudhary Ph.D. (Committee Member); Mike Borowczak Ph.D. (Committee Member); John Emmert Ph.D. (Committee Member) Subjects: Electrical Engineering

PhD, University of Cincinnati, 2021, Engineering and Applied Science: Computer Science and Engineering

Logic encryption, a prominent solution to the hardware IP security problem, protects a circuit by adding 'encryption' logic to lock the design functionality using a set of newly introduced key inputs. Logic encryption for combinational circuits focuses on adding combinational gates as encryption logic. When encrypting sequential circuits, most techniques advocate the modification of the FSM to either prevent entering normal operation or force the design into corrupted state(s) on the application of a wrong key. Another avenue taken by sequential logic encryption is to lock the scan-chains by inserting key gates on the scan connections between the flip-flops in the circuit to reduce the ability to set and observe the internal state of the circuit. Boolean satisfiability based attack methods are successful in decrypting combinational logic encrypted circuits. Subsequently proposed SAT-resilient techniques are susceptible to other type of attacks like removal, bypass or functional analysis attacks. Although SAT methods can be used to attack sequential circuit using scan chains, this approach is rendered ineffective if the scan chains are absent or are locked using key gates, as described above. Due to these limitations, sequential logic encryption techniques claim SAT-resiliency. One of the goals of this dissertation is to test the validity of this claim by developing SAT-based attack methods that can attack logic encrypted sequential circuits without scan access. Circuit unrolling is a promising technique that is used to develop such an attack method. The decryption efficiency of this attack is evaluated against modern sequential logic encryption techniques. Furthermore, more robust and highly effective encryption techniques to counter the sequential SAT attack method are proposed in this work by analyzing the attributes of the attack that contribute towards its success against other sequential logic encryption schemes. Emphasis is placed on extracting information re (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Mike Borowczak Ph.D. (Committee Member); John Emmert Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2020, Engineering and Applied Science: Computer Engineering

In the face of the increasing cost of manufacturing semiconductor devices, many designers of Integrated Circuits (IC) have been electing to outsource the fabrication of ICs to pure play foundries in order to reduce manufacturing costs. However, this may lead to IC designs being stolen, counterfeited, maliciously modified, or otherwise mishandled by bad actors in the supply chain. In response, researchers have devised methods of thwarting such attacks against intellectual property in the IC supply chain. One such method is known as logic encryption. Logic encryption is a hardware security strategy that adds key inputs, which require the correct secret key input, known only to the designer, to be applied for the circuit to have correct output behavior. The field of logic encryption has evolved over the past decade during which increasingly strong attacks and increasingly strong encryption strategies have been developed. However, the cost in terms of power, performance, and area (PPA) of implementing logic encryption has often been ignored in favor of increasing the level of security for proposed methods, and how well they protect against known attacks. Considering these costs is an important hurdle in transitioning the technology to commercial-grade designs, and a strategy for constraining the cost of logic encryption is needed. A methodology for applying known logic encryption methods to a design is proposed in this work. In this methodology, named Constraint-Directed Logic Encryption (CDLE), potential encrypted versions of an IC design are considered. A designer can set the security requirement for encryption as well as power, performance, and area constraints, based on the design specification. There is a subset of designs that meet the security requirement and another that are within the PPA constraints. CDLE targets the overlap of these subsets, and maximizes security within it to produce an optimally encrypted design that meets the security requirement (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); John Emmert Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2017, Engineering and Applied Science: Electrical Engineering

Integrated Circuit (IC) design flow has become a distributive model due to increase in the cost of maintaining fabrication units as transistor technology is advancing. Design industries lose several billion dollars due to miscreants in the fabrication units who try to mishandle the design by pirating or inserting malicious trojans. This has prompted researchers to come up with better design strategies to make it difficult for the attacker to decipher the original functionality of the circuit. Some of the techniques include Logic Encryption, Camouflaging and Split manufacturing. Over the past few years lot of Encryption strategies are being proposed that claims to lock the original circuit with a key scheme making it difficult for the attacker to observe the correct functionality without knowing the correct key scheme. Later, an attack using state of the art boolean satisfiability (SAT) solvers was being proposed which was able to decrypt the above encryption approaches within 10 hours. As SAT is a formal method used for attacking logic encrypted circuits, the key being deciphered is guaranteed to be the correct key and the key verification time is saved. On the other hand, this attack was observed to take exponential time to decrypt circuits with AND trees. This has prompted researchers to exploit this bottleneck to come up with SAT attack tolerant encryption strategies. These approaches tried to add sub-circuits to the original netlist such as AND trees or ones that tried to flip the output for all incorrect key combinations in order to increase the total iterations needed for the SAT attack. Though the current SAT attack thwarting methodologies attempt to add a Hard SAT sub-circuit, they were vulnerable to signal probability skew based attack that could determine the additional sub-circuit being added. Also, all these methodologies had to add sub-circuits to the encrypted netlist. This thesis aims to find sub-circuits within the existing netlist that could (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Wen-Ben Jone Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member) Subjects: Engineering