Doctor of Philosophy (Ph.D.), University of Dayton, 2016, Electrical Engineering

The goal of this research is to develop a method for affordable and reliable sampling and coherent processing of measurement data collected via a modified magnetron oscillator based marine radar system. Non-coherent low-priced marine radar systems offer limited surveillance in clutter rich environments as compared to more expensive and complex coherent solid state radar systems. The approach used herein leverages modern analog to digital converters (ADC) and field programmable gate array (FPGA) technology to affordably and effectively sample the radiated and received signals for further analysis using FFT-based Doppler processing or cross correlation analysis. Track processing of moving targets is fundamental to any advanced radar and is a further focus of this research. The marine radar hardware is modified to capture the transmit signal at the source, and the receive signal at the aperture, for processing via FPGAs. The receive pulse train is cross-correlated with the transmit pulse train reference to remove the uncertainties in the phase history of the collected data. This operation ultimately makes the radar fully coherent on receive. Once the receive signal is made coherent, classical Doppler processing is used to differentiate moving targets from clutter and electromagnetic interference. A real time system has been built on a board with ADCs, FPGAs, and a microprocessor. Mixing of the Transmit (TX) and the Receive (RX) signals, Fourier transform analysis, and Pulse Compression are all executed digitally in the FPGA whereas Doppler Processing is performed on the microprocessor. This paper presents the underlying principles of cohering signals on receive, and it will show a real-time implementation of such algorithms using FPGAs.

Committee: Michael Wicks PhD (Advisor); Lorenzo Lo Monte PhD (Committee Chair); Guru Subramanyam PhD (Committee Chair); Eric Balster PhD (Committee Chair) Subjects: Electrical Engineering; Engineering

Doctor of Philosophy (Ph.D.), University of Dayton, 2021, Engineering

Time-domain back projection (BP) is a widely known method used in Synthetic Aperture Radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, Field Programmable Gate Array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This dissertation presents a new SAR BP algorithm that is tested on a CPU to test the acceleration and functionality and compared with a traditional floating-point based SAR BP algorithm. It is shown that fixed-point based BP algorithm is faster than traditional algorithm and it maintains a high output image quality. The proposed BP algorithm process images with 15.69% speedup on average, while maintaining high quality image outputs. Recently, Intel introduced the Arria 10 FPGA which is the industry's first FPGA that includes single-precision hardened Floating-Point Units (FPUs) on DSP blocks. With the advent of hardened floating-point, FPGA designers have largely abandoned fixed-point processing. Therefore, a series of arithmetic tests are created to evaluate whether fixed-point processing is obsolete considering the FPGA performance. A performance metric is developed to calculate the FPGA performance in terms of logic utilization and kernel speed. All programs are tested with Intel Stratix V FPGA which does not have hardened FPUs and Intel Arria 10 FPGA for comparison. The performance metric indicates that, on average, there is a 20.18% performance increase when Stratix V processes fixed-point operations and 27.17% performance increase when Arria 10 processes fixed-point operations. Even with hardened FPUs, it is shown that the Arria 10 FPGA exhibits a significant logic reduction when processing fixed-point operations. The results clearly indicate that t (open full item for complete abstract)

Committee: Eric Balster Ph.D. (Advisor); Tarek Taha Ph.D. (Committee Member); Russell Hardie Ph.D. (Committee Member); Muhammad Islam Ph.D. (Committee Member) Subjects: Electrical Engineering

Master of Science in Electrical Engineering (MSEE), Wright State University, 2016, Electrical Engineering

Relative to integrated circuit (IC) systems, on-chip fault detection entails determi- nation of whether or not a fault exists. The cause of the fault could be some faulty logic resource or some faulty interconnect (wiring) resource, but typically, fault detection only determines if a fault exists, not what exactly is faulty. Beyond pure fault detection some work has been done relative to on-chip fault analysis to fur- ther determine not only if a fault exists, but exactly what is faulty. Even less work has been done to actually tolerate faulty resources once they have been found. For this work, we take advantage of previous work (ROVING STARS) that detects on-chip faults and analyzes those faults to determine exactly what is faulty. We developed, tested and demonstrated an on-chip technique that takes advantage of dynamic partially reconfigurable field programmable gate arrays (FPGAs) to automatically reconfigure the FPGA for tolerating logic faults.

Committee: John Marty Emmert Ph.D. (Advisor); Saiyu Ren Ph.D. (Committee Member); Raymond Siferd Ph.D. (Committee Member) Subjects: Electrical Engineering

MS, University of Cincinnati, 2005, Engineering : Computer Engineering

Field Programmable Gate Array technology has grown to a stage where entire digital systems with their I/O interfaces can be implemented in single FPGAs. Even so, FPGAs are primarily digital devices with little inbuilt facilities for direct interaction with the analog world. The Multi-Technology FPGA goes beyond this limitation by integrating multi-technology and analog blocks with the regular FPGA fabric. To implement circuits on the MT-FPGA, an automatic configuration bit stream generation system is needed. Designing and implementing such a system has been the point of investigation for this thesis. The major goal in this exercise is to make the system as generic and architecture independent as possible, so as to retarget it to different architectures. The system takes as its input, the output files from FPGA synthesis tools and an architecture specification of the fabric. An XML based architecture specification format and an object-oriented software tool code named “XBits” has been developed. The first part of the thesis explains the specifics of the format and the internals of XBits. Results on academic benchmarks implemented using XBits are also given. As a second part of the thesis, the present MT-FPGA architecture is analyzed for its suitability for large arithmetic circuit implementations. Since the MT-FPGA presents a parallel platform for mapping circuits; signal processing applications that benefit greatly from multiple implementations of functions acting in parallel on long input data streams are of special interest to the MT-FPGA. A new architecture is proposed as a result of this study, which enhances the logic utilization of the FPGA fabric and the speed of arithmetic operations on the MT-FPGA. Associated analysis and comparison of this new architecture with the original architecture is also presented.

Committee: Dr. Karen Tomko (Advisor) Subjects:

Master of Science in Electrical Engineering, University of Dayton, 2024, Electrical and Computer Engineering

Hybrid/Full electric aircraft (HEA/FEA) represents an attractive concept due to its potential to reduce CO2 emissions, decrease fossil-fuel consumption, enhance overall aircraft efficiency, and lower operational costs. As technology progresses towards hybrid/full electric aircraft, the development of high-performance motor drive systems becomes imperative. This necessity introduces new constraints, particularly in low-pressure environments. Designing for high-altitude applications requires careful consideration to prevent issues like partial discharge and power system failures in the air. Converters must exhibit ultra-high efficiency, high power density, and exceptional reliability. While wide band-gap devices, such as Silicon-carbide based Metal Oxide Silicon Field Effect Transistors (SiC-MOSFETs), offer improved switching and high-temperature performance over silicon counterparts, their integration into HEA/FEA applications remains challenging. The high switching speed of SiC-MOSFETs reduces switching losses and facilitates the design of high-density inverters. However, selecting suitable devices is critical for designing high-power-rated inverters. Moreover, the risk of partial discharge increases at high voltages in conditions of low air pressure, posing a threat to inverter longevity by compromising system insulation. This thesis evaluates three distinct inverter/converter topologies comprehensively to determine the optimal circuit topology for HEA/FEA applications. The study explores design strategies to ensure busbar integrity, preventing partial discharge without compromising parasitic control. Throughout the thesis, a three-phase megawatt-scale inverter and a 3.3 kV, 288 A power module are designed, fabricated, and tested to validate the proposed design strategies.

Committee: Cao Dong (Committee Chair); Kumar Jitendra (Committee Member); Ratliff Bradley (Committee Member) Subjects: Electrical Engineering; Engineering

Master of Science in Electrical Engineering, University of Dayton, 2024, Electrical and Computer Engineering

Aircraft electrification provides an effective approach toward tackling the problem of rapidly growing CO2 emissions. Digital twins are a real-time simulation that is synchronized with a particular real instance of a device. Power Hardware-in-the-Loop is another type of real-time simulation that simulates a device, except it is not synchronized with a real device and is used for testing purposes. The design of a power supply for a PHIL system is proposed and designed. The proposed topology is an LLC DC-DC converter with an inverter stage, transformer stage, and active rectifier stage. The procedure started with the design and testing of an FPGA-based controller. FPGA technology was chosen for its ability to perform high-frequency calculations in parallel. In addition to the controller, a gate driver was also designed and tested for the SiC-based inverter stage of the converter. The inverter stage was originally designed as a 3-phase inverter, but is then used as a single-phase inverter for this project. Next, a transformer was designed to interface between the inverter and active rectifier stages. The transformer steps the voltage down from 800V to 60V. Lastly, the GaN-based active rectifier stage was designed and assembled for the secondary side of the transformer. Test results of the GaN devices on the rectifier demonstrate basic switching functionality.

Committee: Dong Cao (Advisor); Raul Ordonez (Committee Member); Jitendra Kumar (Committee Member) Subjects: Electrical Engineering

Master of Science in Engineering, Youngstown State University, 2024, Department of Electrical and Computer Engineering

With technological advancements in the field of wide bandgap semiconductors, the role of (Gallium Nitride) GaN transistors has been contributing significantly to the aspects of higher switching frequency operation with lower switching losses, thereby increasing the efficiency of the device. The study of GaN HEMT devices, due to their higher switching frequency and high-performance semiconducting properties, is a huge topic of interest within the power electronics community, which is why the need for its academic study and research is significant. The CoolGaN™ ™ 600V HEMT half-bridge evaluation board used for this paper is manufactured by Infineon Technologies, featuring a high voltage gate driver IC and up to MHz's range of switching frequency. The Infineon CoolGaN™ 600V HEMT half-bridge evaluation platform is studied for its switching behavior. The GaN device is utilized to explore motor drive applications at different frequency switching conditions, ranging from 50 kHz up to 1MHz. The high-frequency PWM signals are programmed and generated using an Artrix-7 FPGA. An SPWM scheme of control signal generation is digitally implemented in the FPGA. The generated PWM signals from the FPGA are used as the switching gate signal for an and to drive a three-phase gallium nitride inverter with balanced resistive and inductive loads. The output phase voltage and phase current waveforms are monitored and analyzed for their behavior and power factor. The research in this thesis investigates the consequences of employing GaN transistors for high frequency switching in motor drive applications through a combination of studies, simulations, and experiments. This investigation holds significant importance within the realm of industrial power electronics, as it aims to advance efficiency, compactness, and cost-effectiveness across diverse applications.

Committee: Frank Li PhD (Advisor); Vamsi Borra PhD (Committee Member); Pedro Cortes PhD (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy (Ph.D.), University of Dayton, 2024, Engineering

We describe a study on the effect of temperature variations on multi-channel Time to Digital Converters (TDC). The objective is to study the impact of ambient thermal variations on the performance of Field Programmable Gate Array (FPGA)-based Tapped Delay Line (TDL) TDC systems, while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study we choose two devices, Xilinx Artix-7 and Microsemi ProASIC3L. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from -75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved Root Mean Square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. We worked to determine the temperature sensitivity for both FPGA devices by observing a significantly low temperature coefficient using Artix-7, while temperature insensitive and stable performance are achieved using the ProASIC3L device. Total on-chip 3 power of 0.968 W was achieved using Artix-7 while less than 1.988 mW of power consumption was achieved using ProASIC3L device. The results and analysis presented in this study convince that the proposed design using the new generations of the FPGAs would help in the design and optimization of FPGA-based TDCs for many applications.

Committee: Vamsy Chodavarapu (Advisor) Subjects: Electrical Engineering; Engineering; Industrial Engineering

Doctor of Philosophy, The Ohio State University, 2024, Physics

Quantum information science holds the promise of revolutionizing information processing and communication through advancements in quantum computing and quantum communications. Quantum key distribution (QKD) stands out as a method offering unconditional security in communications, particularly with the looming threat that quantum computers pose to traditional cryptographic systems. While existing QKD systems predominantly focus on long-distance communication, future quantum networks are likely to involve the integration of fixed nodes with highly mobile platforms to facilitate the ``last mile'' communication between users. In this dissertation, I present a full system design of a QKD system specifically developed for implementation on highly mobile platforms such as drones and cars. Designing a QKD system for highly mobile platforms poses a formidable challenge, demanding careful consideration of the trade-space of system performance and size, weight, and power (SWaP). In the first part of this thesis, I discuss the design considerations for developing such a platform, culminating in a system using a polarization-based prepare-and-measure BB84 QKD protocol with decoy states. This system is designed with two field-programmable gate arrays, three resonant-cavity LEDs, and off-the-shelf passive optics and detectors. The transmitter platform has a SWaP of 1803 cm^3, 2017 g, and 2453 mW. The receiver has a SWaP of 2728 cm^3, 2678 g, and 5886 mW. The usage of multiple sources can increase the risk of side channel attacks in a QKD system due to the indistinguishability of the quantum states' spectral, temporal and spatial degrees-of-freedom. Other similar studies, have relaxed system security requirements to achieve SWaP metrics with the idea that these attack vectors will be addressed in the future. In this work, great effort is dedicated to ensuring that all sources are as indistinguishable as possible. The remaining distinguishability is quantified as the mutual (open full item for complete abstract)

Committee: Daniel Gauthier (Advisor); Louis DiMauro (Committee Member); David Bromwich (Other); Douglass Schumacher (Committee Member); Jay Gupta (Committee Member) Subjects: Experiments; Physics; Quantum Physics

Master of Science in Engineering, Youngstown State University, 2023, Department of Electrical and Computer Engineering

This research document presents the development of a fully digital controller embedded on a Field Programmable Gate Array (FPGA) for a 50 kW induction heater. The document explores the fundamentals of induction heaters and resonant tank circuits, the operation of the half-bridge inverter unit, and the implementation of phase control techniques. In addition to providing simulation results and a comparative analysis of simulation and hardware implementations, this study demonstrates the practical implications of the developed controller. The research affirms the effective functionality of the fully implemented embedded controller in real-world applications.

Committee: Frank Li PhD (Advisor); Vamsi Borra PhD (Committee Member); Ghassan Salim MS (Committee Member) Subjects: Electrical Engineering

Master of Science in Engineering, Youngstown State University, 2023, Department of Electrical and Computer Engineering

The surging electric vehicle (EV) industry is driving a growing demand for high-performance motor drives as the motor drive systems play a crucial role in an EV's performance and efficiency. Choice of techniques for DC-AC conversion is instrumental in the performance of Voltage Source Inverters (VSI). In this study, a Field Programmable Gate Array (FPGA)-based PWM (Pulse Width Modulation) architecture is proposed for a VSI topology. A variable frequency and soft-starting PWM architecture is proposed for a three-phase induction motor drive. The proposed architecture allows the implementation of Sinusoidal PWM (SPWM) and Space vector PWM (SVPWM) for the control of a three-phase induction motor (TPIM). In this thesis, line-current and phase-voltage characteristics of the TPIM are studied under diferent operating conditions. Simulink is used for the simulation and verifcation of the proposed architecture and experimental results are validated using four-pole squirrel cage TPIM. Harmonic contents for SPWM and SVPWM are studied and superiority of the SVPWM, which can be implemented using the same architecture, is established. Greater DC bus utilization and lower harmonics in SVPWM leads to better performance in terms of power conversion efficiency compared to SPWM. The proposed architecture utilizes a small fraction of the FPGA resources and can be easily integrated into a larger control system architecture. In addition, a PWM generator is designed for high frequency inverters used in wireless inductive power transfer (IPT) applications and is experimentally verifed.

Committee: Frank Li PhD (Advisor); Vamsi Borra PhD (Committee Member); Ghassan Salim PE (Committee Member) Subjects: Electrical Engineering

Master of Science, Miami University, 2023, Electrical and Computer Engineering

Research on division implementations in hardware (HW) is not as well developed as other arithmetic operations, primarily due to a lack of division-based algorithms. This work investigates the efciency of diferent division algorithms as the bit width of the division increases, specifcally for unsigned integer division. Our target architecture is a Field Programmable Gate-Array (FPGA) where we measure each divider's area (measured by Logic Elements of the FPGA) and the speed of division. We investigate non-restoring division, radix-2, radix-4, and Goldschmidt division at widths ranging from 8 bits to 1024 bits. Each of these dividers at each bit-width is tested for functionality and is measured based on speed (a combination of critical path and number of clock cycles to complete) and area (number of logic elements (LEs) needed for the divider). Our results provide a general trend for the area and speed for these division algorithms as the width of the division grows for FPGAs, and our tools are provided open source so that others can implement these dividers with detailed examples for understanding.

Committee: Peter Jamieson (Advisor); Dave Hartup (Committee Member); Chi-Hao Cheng (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2023, Engineering and Applied Science: Computer Engineering

The significant growth in the usage of modern Field Programmable Gate Arrays (FPGAs) can be ascribed to several significant attributes. First, FPGA designs have become simpler and the time-to-market has decreased, thanks to the accessibility of complete development tools, libraries, and IP cores. The expanding FPGA ecosystem and the ability to reprogram FPGAs have made them more accessible and adaptable to the changing industry needs. Second, compared to earlier generations, current FPGAs provide better performance, energy efficiency, and higher degrees of integration. Finally, fresh developments in the fields of Artificial Intelligence, Machine Learning, and IoT (Internet of Things) have boosted the need for adaptable and customized digital circuitry. Thus, it is necessary to enhance the security mechanisms on FPGA designs to combat the compromised FPGA bitstreams/malicious third-party IP blocks or to retrieve the golden designs. To counteract these threats, and to retrieve the lost legacy designs, Reverse engineering (RE) becomes a useful tool. FPGA reverse engineering is a complex process that takes bitstream from the memory of a device as input and outputs a human-readable description of that device. The steps involved in between these endpoints are Bitstream extraction, netlist recovery, and high-level netlist representation. The first step, Bitstream extraction involves retrieving the configuration data from an FPGA. The obtained configured bitstream file is then decoded to re-construct FPGA primitives like Look-Up-Tables (LUTs), Flip-Flops, etc. along with the logical routing connections between them. And this extraction describes the second step, netlist recovery and will be called LUT-level netlist in the rest of the thesis. Finally, high-level netlist representation is the process of understanding the overall functionality of the netlist representing it using Hardware Description Language at a higher abstraction level than the LUT-level netlist. (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Wen-Ben Jone Ph.D. (Committee Member); John Emmert Ph.D. (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2023, Engineering and Applied Science: Computer Engineering

One of the most important tasks in the field of electronic design automation (EDA) is the functional reverse engineering (RE) of flattened Field Programmable Gate Array (FPGA) Look-Up Table (LUT) netlists to their Register Transfer Level (RTL) representation. Legacy designs can be difficult to comprehend since they often lack adequate documentation or the original design files. By converting the netlists to RTL representation, engineers can gain a better understanding of the design's functionality and make improvements or modifications easily. Traditional netlist reverse engineering techniques can be time-consuming and error-prone as they manually examine the netlist and determine the underlying RTL structure. However, recent developments in machine learning, notably in the area of graph neural networks (GNNs), have demonstrated significant progress in addressing EDA issues. In this thesis, we presented a tool RELUT-GNN, that extracts high-level functionality from FPGA netlists using GNNs. To achieve this, a graph representation of the netlist structure is created, with the FPGA leaf cells serving as the nodes and the connected nets serving as the edges. GNNs can efficiently capture the connections and interdependence between the various design aspects by considering the netlist as a undirected graph. To train the GNN, a comprehensive custom dataset is constructed, which contains various data path elements commonly found in FPGA designs, such as Operators, Shifters, Counters, and Finite State Machines (FSMs). The dataset also includes combinations of these elements with varying bit widths, allowing the model to learn the diverse patterns and behaviors of different design components. During training, the GNN learns to aggregate the features of each node along with information from its neighboring nodes. This enables the model to capture the structural characteristics of the netlist and extract the high-level functionality of the sub-circuits with (open full item for complete abstract)

Committee: John Emmert Ph.D. (Committee Member); Ranganadha Vemuri Ph.D. (Committee Chair); Wen-Ben Jone Ph.D. (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2023, Engineering and Applied Science: Computer Engineering

The Boolean satisfiability problem (SAT) is perhaps one of the simplest, yet widely applicable problems in computing. In the context of circuits, SAT algorithms are used to perform a variety of automated reasoning and verification tasks. For example, finding an input set that sensitizes a potential fault is an essential step in Automated Test Pattern Generation (ATPG) which ensures the correctness and reliability of digital circuits. The Davis-Putnam-Logemann-Loveland (DPLL) algorithm forms the backbone of many modern day SAT solvers. It works by guessing the value of a variable, propa- gating the effects of that guess, and backtracking if it realizes the problem cannot be satisfied with such a guess. As a backtracking algorithm, the worst case runtime of DPLL increases exponentially with the number of variables and is a limiting factor for solving larger and more complex problems. Experimental results show that DPLL-based solvers spend the majority of time in the propagation stage, hence speed-up of this stage would have the most impact on the overall efficiency. To accelerate propagation and harness the unique capabilities of Field Programmable Gate Arrays (FPGA) as a computing device, this thesis partitions and packs the initial problem into smaller SAT nodes, which reduces the total number of variables and clauses. With this compacted version, fewer implications steps are required during propagation. The problem is then solved on an FPGA, which uses customized logic to brute-force solve these smaller SAT nodes in a few clock cycles, while CPUs would take hundreds or thousands of cycles. This thesis presents PackSAT, a complete FPGA-based solver targeted for SAT on circuits (CSAT) to showcase the potential FPGAs have in speeding up the propagation stage. PackSAT has been developed using High Level Synthesis and implemented on the Xilinx Alveo U280 Accelerator card. Despite the lack of sophistica (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Boyang Wang Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member) Subjects: Computer Engineering

Master of Science, The Ohio State University, 2023, Electrical and Computer Engineering

Chaotic logic gates, or 'ChaoGates' are a proposed mixed-signal approach to preventing side-channel attacks in hardware networks. These gates are also a fundamental building block for a promising implementation of universal computing, called 'chaos computing'. However, since chaotic systems, by nature, are very sensitive to small disturbances, noise could lead these networks to fail. This thesis discusses the effects of white noise on chaotic networks of Boolean functions (Autonomous Boolean Networks; ABNs). ABNs are a network of interconnected logic gates that display a form of deterministic chaos, explained by a modelling framework based on Boolean transitions, termed Boolean Chaos. I create one such asynchronous, 3-node ABN and measure the output node states at sub-ps timescale. Existing simulation and waveform analyzer tools aren't fast enough to measure the asynchronous, continuously evolving network at the sub-ps timescale. Using a chain of inverter gates instead, I create a delay line with a sampling frequency of 4 GHz. In practice, I make use of a digital computer to reconfigure a field-programmable gate array (FPGA) device to act as the network of Boolean functions. I release the network after setting the initial conditions with a Keypress on the FPGA. As the network evolves over time, I measure its states and transfer the measured data onto the digital computer to further study it using a mathematical model. I observe that the network outputs deterministic, repeated results over the course of 2.5 nanoseconds, beyond which, the errors in the network grow exponentially over time. I continue by demonstrating that the ChaoGate loses dependability before approaching ergodicity, and is only capable of reproducing 11.7% of all possible bit combinations. I conclude by discussing the implications of these results and future work.

Committee: Ayman Fayed (Committee Member); Daniel Gauthier (Advisor) Subjects: Computer Engineering; Electrical Engineering; Engineering

Master of Science in Engineering, Youngstown State University, 2022, Department of Electrical and Computer Engineering

A three-phase variable frequency drive with field-programmable gate array (FPGA) control is investigated in this study. With increasing demands in electric vehicles, electric aircraft, Unmanned Aircraft Systems, and other applications, the high-performance motor drive employing variable frequency control with higher efficiency and reliability is an indispensable part of the ever-changing technological development. The main variable frequency control is based on the sinusoidal pulse width modulation (SPWM) technique with control hardware implemented by using a single FPGA chip. The proposed SPWM control scheme has been realized using a Xilinx Arty A7 development board. The system was tested with a 3-phase Infineon Trench FREDFET technology based on N-channel IGBTs. The control scheme regulates the AC output voltage precisely with a DC power supply. Depending on the operating voltage and frequency, the motor may be able to run above the rated speed to gain extra power. Both simulations and test measurement results are shown.

Committee: Frank Li PhD (Advisor); Pedro Cortes PhD (Committee Member); Vamsi Borra PhD (Committee Member) Subjects: Electrical Engineering; Engineering

MS, University of Cincinnati, 2022, Engineering and Applied Science: Computer Engineering

The rapid increase in the complexities and abilities of Field Programmable Gate Arrays (FP- GAs) and the continual improvement of High-Level Synthesis (HLS) tools to configure FPGAs has led to significant growth in the usage of modern FPGAs in the electronics industry. As a re- sult, there is a need to enhance the security measures on FPGA designs to counter compromised FPGA bitstreams due to either Trojan insertion threats on bitstreams or malicious third-party IP blocks. Reverse Engineering (RE) is a helpful tool to offset these security threats. FPGA reverse en- gineering can be divided into three stages: Bitstream extraction, netlist recovery, and high-level netlist representation. Bitstream extraction is the process of obtaining the bitstream file from an FPGA. In most cases, bitstreams are readily available to the end user, either in encrypted or unencrypted form. The process of recovering different FPGA primitives such as Look- Up-Tables (LUTs), carry modules, Digital Signal Processors (DSPs), flip-flops, and Random Access Memory (RAM) blocks, etc., by analyzing the obtained bitstream and then identifying the connectivity between these primitives to obtain the original netlist is called netlist recovery. The resulting netlist is referred to as a gate-level netlist in the rest of this thesis. The process of identification of high-level modules such as operators, counters, registers, and ALUs from the gate-level netlist and representing it using a Hardware Description Language at a higher level of abstraction than the gate-level netlist is called high-level netlist representation. While there is a significant amount of research done in the field of gate-level to Register-Transfer Level (RTL) reverse engineering of Application Specific Integrated Circuits (ASICs), there is little work done in reverse engineering gate-level FPGA designs. This thesis presents a tool for reverse engineering gate-level F (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member); John Emmert Ph.D. (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2022, Engineering and Applied Science: Electrical Engineering

Boolean Satisfiability (SAT) is an NP-complete problem. It is used in several VLSI design applications such as design automation, design verification and automatic test pattern generation. A SAT solver is an algorithm which checks whether a given SAT problem is satisfiable. There are two kinds of SAT solvers, incomplete and complete solvers. Incomplete solvers are based on iterative stochastic local search (SLS) algorithms, which attempt to solve a set of clauses using randomized variable assignments. These solvers are effective for large problems and use various heuristics to determine the solution. The disadvantage with these types of solvers is that the algorithm usually cannot determine whether the problem is UNSAT and these types of solvers doesn't guarantee to find a solution. Complete solvers use a systematic approach toward exploration. Conflict Driven Clause Learning (CDCL) algorithm is an improved version of the Davis–Putnam–Logemann–Loveland (DPLL) method in which the algorithm learns a new clause from a conflict and performs non-chronological backtracking to the root of the conflict. With this new clause, the algorithm will prevent this branch from being explored again. Over the past few years, Field Programmable Gate Array (FPGA) has been used to solve complex problems due to their superior computational capability. With FPGA's parallel and pipeline processing power and its memory resources, it is an excellent platform to build and run SAT algorithms. This thesis presents a CDCL solver on the Xilinx Alveo U280 Accelerator card, using Vitis HLS. This solver incorporates some of the effective techniques and heuristics used in the modern SAT solvers such as Literal Block Distance (LBD) used for clause pruning, Variable State Independent Decaying Sum (VSIDS) for variable selection heuristics, Phase Saving, Watched Literals, Rapid Restarts (Luby Sequence) and Restart Skips. The FPGA solver is implemented in three different versions with (open full item for complete abstract)

Committee: Ranganadha Vemuri Ph.D. (Committee Member); Wen-Ben Jone Ph.D. (Committee Member); John Emmert Ph.D. (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, University of Toledo, 2022, Engineering

Ever-increasing hardware fabrication costs have compelled the semiconductor industry to utilize the global supply chain by shifting integrated circuit manufacturing overseas. This approach has resulted in several challenges and concerns such as intellectual property (IP) infringement, counterfeiting, reverse engineering, and the introduction of Trojans. Because of the increased demand for integrated circuits (ICs) in different applications, counterfeit circuits and devices can infiltrate crucial infrastructures such as smart grids, military installations, and other critical cyber infrastructures. The usage of counterfeit and compromised devices and chips can cause severe monetary losses and make the security and reliability of the ICs suspect. Physical Unclonable Function (PUF) can ensure the security of ICs by utilizing process manufacturing variations to establish a unique signature and key for the IC chip. These keys have potential use in the generation of secret keys and unique IDs for device authentication. This research presents a comprehensive analysis of the environmental impact on Ring Oscillator PUFs (ROPUFs) design using ten different Xilinx Artix-7 FPGAs. For a comparative study of their performance metrics; three, five, and seven stage configurations of AND-Inverter ROPUFs are implemented. The performance is evaluated in terms of uniformity, reliability, bit-aliasing, uniqueness, and randomness. The impacts of temperature variations, voltage variations, and aging are analyzed in depth for these metrics. The results demonstrate that using a lower number of stages in the Ring Oscillator (RO) promises a better security feature. ROs with a lower number of stages generate higher Challenge and Response Pairs (CRPs). The higher number of CRPs leads to enhanced security. Additionally, this work includes an analysis of two simultaneous environmental variation factors; namely, aging and voltage variations, and temperature variations with voltage variations. The (open full item for complete abstract)

Committee: Mohammed Niamat, PhD (Committee Chair); Richard Molyet, PhD (Committee Member); Weiqing Sun, PhD (Committee Member); Ahmad Javaid, PhD (Committee Member); Noor Ahmad Hazari, PhD (Committee Member) Subjects: Computer Engineering; Electrical Engineering