Master of Science, The Ohio State University, 2019, Electrical and Computer Engineering

This thesis presents work on the development of digital logic gates using Gallium Nitride (GaN) transistors in a 0.25μm process. The allowed minimum width of 12 μm is reduced to 5 μm in order to observe scalability and to measure the performance benefits of smaller device sizes in the GaN process. Due to poor modeling, the designed Buffered FET Logic INV, NOR2, and NAND2 are designed for functionality over performance, resulting from the risk of failure without proper simulations. A preliminary test plan was developed and executed to prove the functionality of the devices across varying temperatures, voltages, and input frequencies, with initial tests indicating that the devices are fully functional across these parameters.

Committee: Waleed Khalil (Advisor); Steven Bibyk (Committee Member); Brian Dupaix (Committee Member) Subjects: Engineering

Master of Science, University of Toledo, 2018, Electrical Engineering

Wide bandgap devices (GaN) are an enabling technology for high frequency and high efficiency power electronics. Especially, the combination of low on-resistance and high breakdown voltages relates to high power-density capabilities of GaN devices and makes them a potential alternative for silicon devices in high power conversion applications. Also, GaN devices are intrinsically very fast with low switching losses due to high saturation velocities and can achieve higher efficiencies in hard switching applications. On the contrary, low inherent capacitance makes them more vulnerable to high dv/dt transitions and can cause undesired circuit level issues such as voltage overshoot, ringing, and false turn-on. Any unchecked external parasitic impedances will further exacerbate the device transient behavior and run the risk of device failure under circuit level implementation. Therefore, this thesis work presents a detailed analytical framework to address some of the circuit level challenges associated with GaN. The analytical framework lays a foundation to optimize device safety and performance. The first part of this thesis work deals with mitigation of false turn-on of the synchronous-FET in a half bridge buck converter operated at 1 MHz frequency. The study presents a detail investigation of false turn-on event and proposes its mitigation by modifying the control-FET gate resistance. An analytical circuit model with intrinsic device components and external parasitic parameters has been considered to develop a relationship between control-FET gate resistance and false turn-on induced voltage of the synchronous-FET. The results of the analytical method proposed in this study show good agreement with the experimental results. The model can then be used to predict false turn-on at varying values of high-side gate resistance. The second part of this thesis focuses on the development of an improved model to predict voltage overshoot in normally-off GaN devices. As t (open full item for complete abstract)

Committee: Raghav Khanna (Committee Chair); Mansoor Alam (Committee Member); Vijay Devabhaktuni (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy (PhD), Wright State University, 2023, Electrical Engineering

Since their invention in 1958, Integrated Circuits (ICs) have become increasingly more complex, sophisticated, and useful. As a result, they have worked their way into every aspect of our lives, for example: personal electronic devices, wearable electronics, biomedical sensors, autonomous driving cars, military and defense applications, and artificial intelligence, to name some areas of applications. These examples represent both collectively, and sometimes individually, multi-trillion-dollar markets. However, further development of ICs has been predicted to encounter a performance bottleneck as the mainstream silicon industry, approaches its physical limits. The state-of-the-art of today's ICs technology will be soon below 3nm. At such a scale, the short channel effect and power consumption become the dominant factors impeding further development. To tackle the challenge, projected by the ITRS (International Technology Roadmap for Semiconductors) a thinner channel layer seems to be the most viable solution. This dissertation will discuss the feasibility of using 2D (two-dimensional) materials as the channel layer. The success of this work will lead to revolutionary breakthroughs by pushing silicon technology to the extreme physical limit. Starting from graphene in 2004, 2D materials have received a lot of attention associated with their distinct optical, electrical, magnetic, thermal, and mechanical properties. In the year 2010, IBM demonstrated a graphene-based field effect transistor with a cut-off frequency above 100 GHz. The major challenge of applying graphene in large-scale digital circuits is its lack of energy bandgap. Other than carbon, a variety of graphene-like 2D materials have been found in various material systems, like silicene, germanene, phosphorene, MoS2, WS2, MoSe2, HfS2, HfSe2, GaS, and InS, etc. Among all the 2D materials, silicene appears to be the most favored option due to its excellent compatibility with standard silicon technology. Simil (open full item for complete abstract)

Committee: Yan Zhuang Ph.D. (Advisor); Ray Siferd Ph.D. (Committee Member); Junghsen Lieh Ph.D. (Other); Marian K. Kazimierczuk Ph.D. (Committee Member); Saiyu Ren Ph.D. (Committee Member); Henry Chen Ph.D. (Committee Member) Subjects: Chemical Engineering; Chemistry; Electrical Engineering; Engineering; Materials Science; Nanoscience; Nanotechnology; Packaging; Physics; Quantum Physics; Solid State Physics

Doctor of Philosophy, The Ohio State University, 2021, Biomedical Sciences

Ewing sarcoma is an aggressive bone and soft tissue-associated cancer affecting pediatric, adolescent, and young adult patients. Despite general improvement in pediatric cancer outcomes due to novel therapeutic options, Ewing sarcoma treatment, which consists of high-dose chemotherapy, radiation, and/or local surgical control, has remained largely unchanged for several decades and patients with metastatic disease continue to see poor outcomes. Although pediatric cancers often have far fewer mutational events than adult cancers, Ewing sarcoma is particularly interesting as the disease is often characterized by a sole chromosomal translocation event: These chromosomal translocations fuse one of the FET protein family members, a group of putative RNA-binding proteins, to a member of the ETS transcription factor family. As these FET/ETS fusion proteins have been determined to function as oncogenic transcription factors responsible for driving Ewing sarcomagenesis, it is critical that the biological mechanisms these fusions utilize to facilitate this process are elucidated. Despite discovery of several FET/ETS translocations, the majority of studies in the field focus on EWS/FLI, as it is the most common fusion observed in patients. Although these studies have provided a breadth of knowledge surrounding oncogenic function of the protein, there is a great deal of uncertainty how alternative FET/ETS fusions should be diagnosed and treated in the clinic. Herein, we characterize a novel FET/ETS fusion and perform the first comparative analysis on EWS/FLI and alternative, rarer FET/ETS fusion proteins. Our results reveal general similarities in DNA-binding and transcriptional regulation properties between the broad FET/ETS fusion group and provide the first tangible body of evidence to support that these fusions should indeed be classified as bona fide Ewing sarcoma tumors. Furthermore, we sought to characterize contributions of the FLI protein to overall EWS/FLI funct (open full item for complete abstract)

Committee: Stephen Lessnick MD/PhD (Advisor); Timothy Cripe MD/PhD (Committee Member); Lawrence Kirschner MD/PhD (Committee Member); Mark Parthun PhD (Committee Member) Subjects: Biomedical Research; Cellular Biology; Molecular Biology; Oncology

Doctor of Philosophy, Case Western Reserve University, 2020, Physics

Within the past decade or so, semiconductor physics has turned a keen eye on two dimensional systems, with the pivotal investigation of atomically thin carbon films. The remarkable figures of merit produced by graphene in electronic and electrochemical applications, in contrast to bulk carbon properties, are indicative of the potential that layered materials might possess in their own right. Transition metal oxides offer a relatively unexplored facet of 2D semiconductor technology; these materials are often overlooked due to their wide band gaps when considering new subjects for nanostructure study. However, oxides offer a library of interesting properties, many of which are still not fully understood, and can be easily modified through doping to engineer new characteristics. Herein, three studies are discussed, where characterization of layered oxides, modified via various methods of doping, result in unique behaviors. The first study involves varying oxygen stoichiometry in α-MoO3, where transport is controlled by quantifiable reduction of grown α-MoO3 nanoflakes. The second details the study of LixCoO2, the staple cathode material used in lithium-ion batteries. This material exhibits unique charge-ordering phenomena as a function of lithium content, and is explored in its few-layer, single-crystal form for the first time. Finally, V2O5 is investigated, which displays p-type characteristics and a surface scattering effect when partially doped with sodium. The band structure is analyzed to explain these behaviors. The findings of these studies may play a key role in engineering thin oxide systems for future electronics applications.

Committee: Xuan Gao Professor (Advisor); Walter Lambrecht Professor (Committee Member); Jesse Berezovsky Associate Professor (Committee Member); Alp Sehirlioglu Associate Professor (Committee Member) Subjects: Condensed Matter Physics; Materials Science; Physics

Doctor of Philosophy, The Ohio State University, 2017, Electrical and Computer Engineering

Electron-plasmonic devices are of strong interest for terahertz applications. In this work, we develop rigorous computational tools using finite difference time domain (FDTD) methods for accurate modeling of these devices. Existing full-wave-hydrodynamic models already combine Maxwell's and hydrodynamic electron-transport equation for multiphysical hybrid modeling. However, these multilevel methods are time-consuming as dense mesh is required for plasmonic modeling. Therefore, they are not suited for design and optimization. To address this issue, we propose new iterative ADI-FDTD-hydrodynamic hybrid coupled model. The new implementations provide time-efficient, yet accurate, modeling of these devices. It is demonstrated that for a typical simulation, up to 50% reduction in simulation-time is achieved with a nominal 3% error in calculations. Using the new tool-set, we investigate several devices that operate using the properties of 2D electron gas (2DEG). We provide one of the first multiphysical numerical analyses of these devices, giving accurate estimates of their terahertz performance. The developed tool allows simulation of arbitrary 2DEG based terahertz devices, providing useful and intuitive 2D field information. This has allowed understanding of the operation and radiation principles of these devices. Specifically, we examine the known plasma-wave instability in short-channel high electron mobility transistors (HEMTs) that leads to terahertz emissions at cryogenic temperatures. We also examine terahertz emitters that exploit resonant tunneling induced negative differential resistance (NDR) in HEMTs. Finally, using this tool we numerically demonstrate the existence of acoustic and optical-plasmonic modes within 2DEG bilayer systems in HEMTs. Methods for exciting and controlling these modes are also discussed enabling new physics among bilayer devices.

Committee: John Volakis (Advisor); Siddharth Rajan (Advisor); Kubilay Sertel (Committee Member); Teixeira Fernando (Committee Member); Niru Nahar (Committee Member); Karin Musier-Forsyth (Committee Member) Subjects: Electrical Engineering; Plasma Physics

Master of Science, The Ohio State University, 2015, Electrical and Computer Engineering

Perovskite oxides are an interesting group of materials with diverse and unique electronic, photonic, optical and magnetic properties. One of the recent discoveries in perovskite oxide is the extreme high electron density at polar and non-polar oxide heterojunction interfaces. GdTiO3/SrTiO3 heterostructure shows an electron density of 3x1014 cm-2 at the interface that is around one order higher than any conventional semiconductor heterostructures. In this work, GdTiO3/SrTiO3 heterostructures were used to demonstrate field effect transistors. This is the first demonstration of transistor with such high charge density. We also investigated the factors that limit the charge modulation in this heterostructure, and developed an analytical model that can predict charge control characteristics of this heterostructure. Three methods were proposed and demonstrated to improve the modulation, leading to record charge modulation of 1.5x1014 cm-2, which is the highest to date for any semiconductor system using electronic gating.

Committee: Siddharth Rajan (Advisor); Betty Anderson (Committee Member) Subjects: Electrical Engineering; Materials Science; Nanotechnology; Solid State Physics

Master of Science, University of Toledo, 2014, Electrical Engineering

The purpose of this research is to test various output parameters of gallium nitride transistors. These include the voltage-current characteristic, drain-source leakage current, dv/dt immunity, and resistance to single events and radiation hardness. The specific gallium nitride transistors tested are enhancement (normally-off) devices from Efficient Power Conversion (EPC) Corporation. These devices are in passivated die form, with land grid array solder bars. For the voltage-current characteristic, the gallium nitride device was mounted on a printed circuit board. The characteristic was compared to that of conventional devices, such as silicon and silicon carbide, at low and high temperatures. The voltage-current characteristic of gallium nitride shows an on-resistance lower then silicon or silicon carbide devices. Gallium nitride devices are also found to saturate at far lower drain-source voltages than the example silicon and silicon carbide devices, and require a lower gate voltage to turn on fully, which means that lower supply voltages are necessary to take full advantage of the device. The gallium nitride characteristic did have a greater sensitivity to temperature than the conventional devices, however. The drain-source leakage current of gallium nitride devices was also compared to conventional devices, from low to high temperatures. The leakage current for gallium nitride devices was many orders of magnitude higher than the conventional devices tested, and even though leakage current increases with increasing temperature for all the devices tested, the magnitude of the leakage currents associated with gallium nitride devices mean that they may make very good temperature sensors. Gallium nitride has superior dv/dt immunity when compared to conventional devices. The device tested withstood a dv/dt magnitude that was double the maximum dv/dt the conventional devices could withstand. The theoretical dv/dt immunity level of gallium nitride device (open full item for complete abstract)

Committee: Daniel Georgiev (Committee Chair); Vijay Devabhaktuni (Committee Member); Roger King (Committee Member) Subjects: Electrical Engineering

MS, University of Cincinnati, 2009, Engineering : Electrical Engineering

As device dimensions continue to shrink into the nanometer length regime, conventional complementary metal-oxide semiconductor (CMOS) technology will approach its fundamental physical limits. Further miniaturization based on conventional scaling appears neither technically nor economically feasible. New strategies, including the use of novel materials and one-dimensional device concepts, innovative device architectures, and smart integration schemes need to be explored. They are crucial to extending current capabilities and maintaining momentum beyond the end of the technology roadmap. Semiconducting nanowires are an attractive and viable option for channel structures. By virtue of their potential one-dimensionality, such nanoscale structures introduce quantum confinement effects, thus enabling new functionalities and device concepts. In this thesis we study performance limits of Indium Arsenide nanowire Field Effect Transistors (InAs NWFETs) in a Gate All Around (GAA) structure and examine its upper limits of performance. InAs in particular is an attractive candidate for NW-based electronic devices because of its very high electron mobility at room temperature of 30,000 cm2/Vs in comparison to silicon's mobility of 1480 cm2/Vs. The device simulations were carried out using MultiGate Nanowire (Nanowire MG) simulator made available at NanoHUB (www.nanohub.org) by Network for Computational Nanotechnology (NCN). The InAs NWFET was simulated for variations in channel diameter, channel length, oxide thickness and the corresponding Id – Vg characteristics were analyzed. Short Channel Effects (SCEs) namely Drain Induced Barrier Lowering (DIBL) and threshold voltage roll off were studied. Sub-threshold slope and ON/OFF current variations were analyzed for variations in device dimensions. Finally the device characteristics of Silicon Nanowire Field Effect Transistors (Si NWFETs) were simulated for the same variations in channel diameter, channel length and oxide thickness (open full item for complete abstract)

Committee: Kenneth Roenker PhD (Committee Chair); Marc Cahay PhD (Committee Member); Punit Boolchand PhD (Committee Member) Subjects: Electrical Engineering

MS, University of Cincinnati, 2006, Engineering : Electrical Engineering

Carbon nanotubes have generated much interest in the last few years for application in electronic devices because of their demonstrated ability to serve as a possible alternative to silicon technology for fabrication of nanoscale electronic devices, in view of the challenges faced by the continuous scaling of existing silicon technology. Much effort has been applied into the understanding of the underlying principles and the device physics of carbon nanotubes as also in the fabrication of suitable devices with various geometries. The current simulation approaches used for generating reliable device characteristics for these devices can be highly complex and are most often computationally intensive. There is, therefore, a need to develop alternative approaches that are simple and computationally less intensive and yet adequately accurate, especially in the context of design and evaluation of circuits using these devices. In this thesis, we have performed a detailed study of the working principles of semiconducting carbon nanotubes with the objective of developing compact models that can replicate, with good accuracy, the current-voltage characteristics of these devices. Specifically, compact models have been developed for the current - voltage characteristics for the cylindrical gate Schottky-Barrier Carbon Nanotube Field Effect Transistor (SB-CNFET), consistent with experimental results published in the literature. These models reflect the dependence of the transistor characteristics on various physical parameters such as different dielectrics and different gate insulator thicknesses. These compact models can be readily integrated into any of the existing Hardware Description Languages for building and evaluating circuits based on SB-CNFET or hybrid CMOS/ CNFET technology.

Committee: Dr. Harold Carter (Advisor) Subjects:

Doctor of Philosophy, The Ohio State University, 2012, Electrical and Computer Engineering

Handheld devices, such as cellphones, dominate consumer electronics market today and are foreseen to grow further in future years. One of the primary challenges with these devices is reducing the power consumption while keeping the operating frequencies high. Scaling of transistor dimensions has contributed to both increasing chip operating frequencies and greater functionality per unit area. However, as dimensions enter a few 10's of nanometer, leakage currents have also increased, escalating the overall power consumption. Scaling of supply voltage is a key to keep both dynamic and static power consumption low. Tunneling-based devices are investigated to address this challenge. Tunnel diodes in conjunction with conventional transistors can be used in novel circuit topologies to develop high speed circuits operating below 0.5V. However, large scale manufacture requires a Si-based device structure that can be fabricated with tools compatible with standard CMOS processing. In this dissertation, Si-based resonant interband tunnel diodes (RITD) are fabricated using chemical vapor deposition (CVD). High peak to valley current ratio's (PVCR) of 5.2 are obtained through optimization of the boron δ-doping with peak current densities of 20 A/cm2. This is the largest PVCR for silicon based tunnel diodes fabricated using CVD. Further, integration into a standard electronic design automation (EDA) tools is essential to enable development of very large scale integrated (VLSI) circuits. Tunnel diodes have been integrated into the Cadence EDA tool and a 32 x 32 bit tunneling SRAM (TSRAM) memory array has been designed with a standard 90 nm product development kit (PDK) obtained from MOSIS, for use as embedded memory. This provides a platform to compare TSRAM performance with the currently dominant SRAM and embedded DRAM technologies. Its performance and robustness to process variation is evaluated for a supply voltage of 0.5V. Read access times of 1 ns and write access times of (open full item for complete abstract)

Committee: Paul Berger (Advisor); Marvin White (Committee Member); Patrick Roblin (Committee Member) Subjects: Electrical Engineering

Master of Science, The Ohio State University, 2012, Electrical and Computer Engineering

Aluminum Oxide (Al2O3) is a high k dielectric material with promising biosensor applications. The key feature of the Al2O3 device that allows its stable operation in high salt buffers is the impermeability of the device to mobile buffer ions. Permeation of such mobile buffer ions into traditional silicon-based device results in electrical instability of the device of magnitudes sufficient to interfere with analyte sensing. This thesis focuses on Al2O3 high k dielectric devices which could work in the physiologic buffer solution (PBS). A low cost Al2O3 MOS capacitor was first fabricated and tested as a tractable model for metal-oxide-semiconductor field effect transistor (MOSFET). The MOS capacitors were dipped in sterile PBS solution for increasing intervals of time starting from 30 mins upto 24 hours. Triangular voltage sweep (TVS) method was used to characterize the Na+ ion penetration. No sodium ion (Na+) penetration was observed for the Al2O3 capacitors. By contrast, the dose of Na+ ion penetration into silicon-dioxide MOS capacitor increased with increasing soak time in the PBS solution. Further, no Na+ ion response was observed for varying Al2O3 thickness of 10nm, 25nm, 50nm, 100nm. A low cost Si based bioFET with 20nm high-k Al2O3 dielectric deposited by ALD was fabricated and tested in the PBS solution later. After fully functionalizing the surface with aminopropyldimethylethoxysilane (APDMES), the Al2O3 gate dielectric bioFET is capable to work under PBS solution. The drain to source current decreased after detecting the streptavidin. This could be the mobile charge in the channel decreased after binding of the protein. However, the decreased changes are very small and cannot be used as an effective biosensor. To some extent, these changes could be noise because the common source I-V measurements were done in solution which increases lots of unstable factors.

Committee: Paul Berger (Advisor); George Valco (Committee Member) Subjects: Electrical Engineering

Master of Science (MS), Ohio University, 1991, Electrical Engineering & Computer Science (Engineering and Technology)

A small-signal modeling of GaAs FET and broad band amplifier design

Committee: Ebrahim Mokari (Advisor) Subjects:

Master of Science (MS), Ohio University, 1991, Electrical Engineering & Computer Science (Engineering and Technology)

Noise analysis of multiport networks containing GaAs FETs based on measured data or physical FET parameters

Committee: Ebrahim Mokari (Advisor) Subjects: