Doctor of Philosophy, The Ohio State University, 2020, Electrical and Computer Engineering

A novel design theory for dual-input Doherty power amplifiers (PAs) is first presented in this dissertation, in which the auxiliary transistors do not fully turn off at backoff power. Given the input design variables selected by the PA designer, a Doherty load modulation scheme is exactly implemented at the current-source reference planes of the transistors by solving for the characteristic impedance of the Doherty quarter-wave transformer and the resistance of the common load. The Doherty output combiner at the package reference plane that sustains the desired dual-input DPA performance is then synthesized using nonlinear embedding technique and built with a lossless and reciprocal passive circuit. Then an analytic theory for dual-input outphasing power amplifiers that incorporates in one unified treatment the continuum of solutions for power combining including the Doherty and Chireix modes is presented. This unified theory developed at the current source reference planes reveals the performance trade-off achieved by all of the possible PA combiners within the continuum of solutions. Moreover, it identifies novel types of dual-input hybrid Chireix-Doherty (HCD) and hybrid Doherty-max (HDmax) PAs that combine key features of the Doherty and Chireix operations such that the fundamental drain voltages applied to both the main and auxiliary transistors remain constant versus output power levels. As a result, these two hybrid PA modes achieve the maximum flat efficiency response versus power, in contrast to the efficiency drop observed between backoff and peak in a conventional Doherty PA. Finally, a new type of wideband dual-input hybrid Doherty outphasing PA (HDO-PA) is developed in which the load-modulation continuously slides from the HDmax PA mentioned above to the conventional Doherty PA mode as the frequency increases. For a symmetric HDO-PA implementation, this corresponds to the peak-to-backoff fundamental voltage ratio of the auxiliary amplifier linear (open full item for complete abstract)

Committee: Patrick Roblin (Advisor); Waleed Khalil (Committee Member); Kubilay Sertel (Committee Member); Stephanie Moulton (Other) Subjects: Electrical Engineering

Master of Science, The Ohio State University, 2022, Electrical and Computer Engineering

A novel broadband Doherty Power Amplifier (DPA) design for 4G applications is presented with the aid of a modified version of DPA Graphical User Interface (GUI) Tool. Compared to the previous version, the new GUI uses Output Back-Off (OBO) as the input instead of the peak power ratio of the DPA Main and auxiliary PAs. Furthermore, the load impedance seen by the Main PA (MPA) at 2nd harmonic and 3rd harmonic can be directly controlled from the GUI. In this design, Main PA is operated under class F mode and the auxiliary PA is operated under Class C mode. The main PA is biased at -3.2 V at the gate (lower than typical values: -2.7 V ~ -3 V) to boost the efficiency. A new parasitic network with simple structure is extracted using OSU Embedding Model. Design procedures are stated as follows. Fundamental load impedances seen by both PAs are generated by GUI at Current source Reference Plane (CRP). Then, the Output Matching Network (OMN) is synthesized at CRP for both PAs separately. At last, the input matching network and the equal split Wilkinson power divider are designed to realize the broadband DPA. Electromagnetic (EM) Co-simulation result shows the DPA achieves 59.4-62.2% drain efficiency at 8-dB OBO at 1.5-2.2GHz with a gain of 10-13dB. The peak power range is between 43.7 dBm and 44.5 dBm. The THD and IM3 is around -15dB at back off power. The performance of the proposed DPA iii design is shown to be comparable to state-of-the-art designs, which indicates our DPA has a good performance.

Committee: Patrick Roblin (Advisor); Wladimiro Villarroel (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 0, Electrical and Computer Engineering

This dissertation presents a novel 2-input 3-Way architecture and design methodology for dual-band Doherty power amplifiers to be referred as 3-Way DB-DPA. It also presents a new digitally controlled 4-input 3-Way DB-DPA that is based on the 2-input 3-Way DB-DPA. The 3-Way DB-DPA consists of two main amplifiers, one for each band, and an auxiliary amplifier handling both bands. This new 3-Way DB-DPA enables the average drain efficiency in concurrent dual-band operation to be improved compared to the traditional 2-Way DB-DPA by avoiding early clipping in the main amplifiers while benefiting from load-pulling from the auxiliary PA. The improvement of the 3-Way DB-DPA has been verified in theory and simulation at the current- source reference plane (CSRP) as well as in measurement, with a fabricated PA. A statistical analysis using 2D CW signals with LTE probability distribution functions (PDF) is performed for the new PA's architecture at the CSRP, which demonstrates an improvement in the concurrent average efficiency by 15 points, compared to the conventional 2-Way DB-DPA. In 2-input 3-Way DB-DPA non-concurrent operation, the measured CW drain efficiency in the lower-band (1.5 GHz) is 82.8% at peak and 66.6% at 9.6 dB backoff; for the upper-band (2.0 GHz), 70.0% at peak and 48.4% at 9.4 dB backoff. In 4-input 3-Way DB-DPA non-concurrent operation, the measured CW drain efficiency in the lower-band (1.5 GHz) is 81.5% at peak with optimal out- phasing angle ∆φ=172◦, and 67.4% at 8.7 dB backoff with ∆φ=166◦, and for the upper-band (2.0 GHz), 66.7% at peak with ∆φ=−57◦, and 59.8% at 8.5 dB backoff with ∆φ=−67◦. The CW concurrent-balanced drain efficiency reaches 66.2/52.0% in the 2-input 3-Way DB-DPA at 3/6 dB backoff. The 2-input 3-Way DB-DPA is also tested with modulated signals. In single-band operation, at 1.5 and 2.0 GHz the aver- age power and average drain efficiency after DPD are 31.2/33.4 dBm and 50.4/41.2%, for an OFDM/LTE signal with 10 MHz bandwidth and 9.5 (open full item for complete abstract)

Committee: Patrick Roblin (Advisor); Tawfiq Musah (Committee Member); Kubilay Sertel (Committee Member); C.K. Shum (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 2014, Electrical and Computer Engineering

A fully model-based nonlinear embedding device model including low and high-frequency dispersion effects is implemented for the Angelov device model and successfully demonstrated for load modulation power amplifier (PA) applications. Using this nonlinear embedding device model, any desired PA mode of operation at the current source plane can be projected to the external reference planes to synthesize the required multi-harmonic source and load terminations. A 2D identification of the intrinsic PA operation modes is performed first at the current source reference planes. For intrinsic modes defined without lossy parasitics, most of the required source impedance terminations will exhibit a substantial negative resistance after projection to the external reference planes. These terminations can then be implemented by active harmonic injection at the input. It is verified experimentally for a 15 W GaN HEMT class AB mode that using the second harmonic injection synthesized by the embedding device model at the input, yields an improved drain efficiency of up to 5% in agreement with the simulation. An asymmetric Doherty amplifier was built using two 15Wpeak power packaged GaN transistors for the demonstration of the proposed method. 71% drain efficiency at the peak power of 41.8 dBm and 62.7% at the second peak of 32.8 dBm (9 dB back-off) were observed. Above 50% drain efficiency was maintained over the 11 dB output power range. 51.86% average drain efficiency was observed after linearization maintaining -51.46 dBc adjacent channel power ratio excited by 10 MHz bandwidth long term evolution signals with 9.96 dB peak to average power ratio. A novel procedure was introduced for designing Doherty amplifiers using the model based nonlinear-embedding technique. First, the Doherty intrinsic load matching network is designed at the transistor current-source reference-plane with the main and auxiliary devices interconnected. Identical devices with different biasing are used (open full item for complete abstract)

Committee: Patrick Roblin (Advisor); Roberto Rojas-Teran (Committee Member); Steven Bibyk (Committee Member); Christopher Hadad (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 2007, Electrical Engineering

Nowadays there has been increasing demand for radio frequency (RF) power amplifiers (PAs) to have high efficiency so as to extend wireless terminal's battery/talk time and achieve low form-factor in mobile, as well as reduce the cooling and electrical power cost in base stations. The classical design equations of efficient switching-mode class E PAs have been challenged by non-ideal issues which can lead the analysis of class E PAs to be enormously complex and intractable. In this work, the design of class E pHEMT PA has been improved based on the ADS load-pull simulation, which permits an iterative search for the nominal impedance values that maximize efficiency and output power under various bias/load conditions of the active transistor. An important contribution of this dissertation is the proposed multi-harmonic real-time active load-pull (RT-ALP) based on the large signal network analyzer (LSNA), for designing high efficiency non-linear PAs. It applies real-time tunings at the second and third harmonic frequencies, which enable to quickly synthesize a wide range of harmonic load reflection coefficients without stability issue due to open-loop structure. Fast acquisition of reliable large-signal data generates the RF dynamic loadlines, PAE and power contour plots for guiding the design of non-linear PAs. A GaN HEMT demonstrats a PAE of 81% (class F) at 2 GHz by tuning up to the third harmonic. Based on the predicted optimal impedances, a pHEMT PA is designed and constructed with matching networks achieving 68.5% PAE at 2 GHz, further demonstrating the efficacy and reliability of the proposed multi-harmonic RT-ALP for the interactive design of power efficient PAs. An integrated CMOS Doherty PA for 3.5 GHz WiMAX is designed using the 0.18µm TSMC CMOS. Cascode transistors are chosen to achieve high efficiency and address the low breakdown voltage issue. Lumped components replace the λ/4 transmission line for circuitry miniature. The layout passes all the DRC/LVS ch (open full item for complete abstract)

Committee: Patrick Roblin (Advisor) Subjects: