Master of Science in Engineering (MSEgr), Wright State University, 2010, Electrical Engineering

In this work we present the design and characterization of a parameterizable Digital Single Sideband Modulator (DSSM) circuit for use with a Digital Radio Frequency Memory (DRFM) or other signal processing circuits. Field Programmable Gate Arrays (FPGAs) can be used as a prototyping platform for quickly verifying and hardware testing a digital circuit or system. FPGAs can also be used as an implementation platform for a digital circuit or system. A main advantage of FPGAs over that of an Application Specific Integrated Circuit (ASIC) is that it can be quickly (and often dynamically) reprogrammed; whereas an ASIC can take months to fabricate. Currently there is limited capability to quickly and easily generate backend digital signal processing systems for electronic warfare (EW) applications for implementation on an FPGA or an ASIC platform. It is advantageous (especially for dynamically reprogramming FPGAs) for backend EW processing to have parameterizable hardware description language (HDL) code to assist in quickly implementing digital processing capabilities for EW systems. The purpose of this thesis work is to provide just such a capability. We present a completely generic VHDL digital single sideband modulator (DSSM) based on a parameterizable Hilbert Transform (HT). We characterize and test the code so that the user can quickly implement a system to meet their expectations. The entire system is described in VHDL to provide an inexpensive, long term, portable, and parameterizable solution which allows for rapid design and redesign of DSSM circuits. This design is technology portable so it will be viable now and in the future for rapid prototyping, demonstration, and implementation. So as technology changes this code transitions with it. The DSSM via HT rapidly delivers digital circuits for FPGA or ASIC radar or other EW applications.

Committee: Marty Emmert PhD (Advisor); Saiyu Ren PhD (Committee Member); Raymond Siferd PhD (Committee Member) Subjects: Electrical Engineering; Engineering

Master of Science in Bioengineering, University of Toledo, 2007, Bioengineering

The field of neuroscience has grown tremendously in the last twenty years due to advancements in instrumentation. It is now possible to electrically stimulate individual or groups of neurons, and record the results with electrodes and optical imaging techniques. Current methods to control instrumentation using waveform generation encounter many difficulties including cost, complexity, lack of customization, and multiple components to generate complex waveforms. Therefore, it would be advantageous to design a multichannel waveform generation device that can provide analog or digital signals with customizable on times, off times, delays, amplitudes, and number of cycles. A functional Direct Digital Synthesis (DDS) system was developed using a C programmed microcontroller. To begin, parameters were entered in Matlab, and microcontroller timers generated a TTL pulse using an internal oscillator to control the parameters of the waveform. An analog switch selected whether the signal entered a circuit to output a sine or square wave. If a sinusoid was selected the waveform was developed using a frequency divider and eighth order Bessel filter. The original digital or newly formed sine waves were amplitude adjusted using operational and programmable gain amplifiers. The signal was directed to the proper output channel by a set of eight analog switches addressed by a demultiplexer. This accuracy of the digital waveforms was compared with a function generator using an equal duty cycle with a range of times between 0.1ms and 1s, and the waveforms were found to be identical in timing characteristics and amplitude. The ability to generate irregular digital pulses was also tested, and the resolution was excellent over the same timing range. A sinusoid was generated using the Bessel filter and the signal was found to be clean and accurate in amplitude and frequency. The additional requirements of variable initial delay, finite number of pulses, and the ability to output from one o (open full item for complete abstract)

Committee: Scott Molitor (Advisor) Subjects: