MS, Kent State University, 2024, College of Arts and Sciences / Department of Computer Science

Cryptography, derived from the Greek word meaning "to hide information," involves techniques for converting readable plaintext into unreadable ciphertext through a process called encryption. Cryptography algorithms are broadly categorized into two types: symmetric key cryptography and asymmetric key cryptography. Symmetric key cryptography is further divided into block ciphers and stream ciphers. Block ciphers, based on their structure, can be classified into two main categories: Substitution-Permutation Networks (SPN) and Feistel Networks (FN). This research focuses on SPN-based block ciphers. In 1949[1], Claude Shannon introduced two fundamental operations required for a robust cryptosystem: substitution and permutation. Substitution, the core component of SPN-based cryptography, is implemented through substitution boxes (S-Boxes), where each element in the plaintext is mapped to another element to achieve nonlinearity and provide the confusion property crucial for security. With the rise of constrained devices, such as the Internet of Things (IoT), there is an increasing demand for lightweight symmetric-key algorithms. However, in many cases, the S-Box contributes the most to the hardware complexity and computational load compared to other linear components. This research addresses this challenge by designing and optimizing a lightweight cryptosystem suitable for resource-limited environments. The thesis makes two key contributions to the field of lightweight cryptography. The first contribution is the development of chaos-based S-Boxes tailored for devices with restricted computational capabilities. By leveraging chaotic maps, the proposed S-Boxes achieve a high degree of nonlinearity and security while maintaining a minimal computational and hardware footprint, making them ideal for IoT and other constrained devices. These chaos-based S-Boxes introduce dynamic, unpredictable substitution patterns that enhance resistance to cryptanalysis techniques such as l (open full item for complete abstract)

Committee: Maha Allouzi Dr (Advisor); Younghun Chae Dr (Committee Member); Lei Xu Dr (Committee Member) Subjects: Computer Engineering; Computer Science

MS, University of Cincinnati, 2013, Engineering and Applied Science: Computer Engineering

Cryptographic hardware is now widely deployed in everything from pay TV units to cell phones and Smart cards. Smart cards are most often used as cryptographic devices to provide strong authentication of users and to store secret information securely. The compromise of this private data or the hardware which guards it can have disastrous implications including loss of privacy, forged access, or direct monetary theft. These cryptographic devices are easily obtainable and attackers can carry out attacks on the system without directly attacking the mathematics of the algorithms. This thesis talks about a class of such practical "implementation attacks" on cryptographic hardware devices called "Differential Power Attacks". Differential Power Analysis (DPA) attacks area a powerful side channel attack that can be mounted easily to reveal secret key. It exploits data dependency of cryptographic circuits on power consumption with statistical analysis to figure out the secret key. These attacks are very common since device can be easily attacked without any knowledge of implementation.

Committee: Ranganadha Vemuri Ph.D. (Committee Chair); Wen Ben Jone Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2012, Engineering and Applied Science: Computer Engineering

The revolution brought by the advancement in Integrated Circuits (IC) technology has resulted in an exponential increase in the use of smartcards and other cryptographic devices for several security-centric applications like digital signatures, identification and secure communication. This growing dependency on electronic devices for critical applications has led to increased sophistication of hardware attacks on ICs, resulting in the need for effective hardware implementation of cryptographic algorithms. Cryptographic algorithms, in spite of being mathematically secure, lose their potency when implemented in hardware due to data leakage at the hardware level through channels like power consumption, timing delay and Electromagnetic emanation. Attacks based on such leakage channels are commonly referred to as Side Channel Attacks (SCA). Differential Power Analysis (DPA) is a sophisticated SCA method that breaks a cryptographic circuit by correlating the power consumption and the applied inputs. DPA based attacks exploit a fundamental weakness in current ASIC design methodologies (SCMOS), where the power consumption is dependent on the applied inputs. Several countermeasures have been proposed at the circuit level to prevent DPA attacks. Secure Differential Multiplexer based Logic using Pass Transistors (SDMLp) is one such countermeasure designed at Digital Design and Environments Lab at University of Cincinnati. In this thesis, we propose a Synthesis Flow for DPA resistant circuits using Binary Decision Diagrams for the SDMLp logic style. Using the proposed design flow, we achieve an average area reduction of 35% and power saving of 30% albeit with a delay penalty of 20% compared to existing secure libraries. We also show that the maximum instantaneous current variance (security metric) is 40 times better for the proposed synthesis flow than existing synthesis techniques for other secure libraries (WDDL).

Committee: Ranganadha Vemuri PhD (Committee Chair); Wen Ben Jone PhD (Committee Member); Carla Purdy PhD (Committee Member) Subjects: Computer Engineering

MS, University of Cincinnati, 2007, Engineering : Computer Engineering

In recent times, many embedded applications such as mobile phones, smart-cards, etc. use cryptographic devices that use a secret key to encrypt sensitive data to secure it. Encryption algorithms are often challenged during physical implementation (ICs), providing key information to the attackers. Differential Power Analysis (DPA) is a power attack technique uses the difference in power consumed by each input data in conjunction with statistical analysis to extract statistical information that correlates power consumption to the secret key. Our goal is to present a Dynamic Differential Logic style whose power consumption is input independent and which reuses part of circuit to generate differential output. The logic style proposed by us, Reduced Complementary Dynamic and Differential logic (RCDDL) style helps achieve increased DPA resistance with 31.66% improvement in security strength, 14% reduction in power and 7.75% reduction in area on an average when compared to other existing logic styles.

Committee: Dr. Ranga Vemuri (Advisor) Subjects: