Master of Science, The Ohio State University, 2023, Electrical and Computer Engineering

Over the past decade, there has been a growing movement towards reducing the carbon footprint which involves striving for net-zero emissions and developing an infrastructure that can sustain it. Among the end-use sectors, transportation accounts for nearly a third of overall greenhouse gas (GHG) emissions, with commercial vehicles as a huge contributor, making it imperative for this industry to adapt to emerging technologies to accommodate the expectations of a green and sustainable mobility vision. Battery electric and fuel cell vehicle technologies are suitable candidates to replace the existing conventional fossil fuel powered vehicle architectures but a complete transformation is nigh realizable due to various impediments. A soft impact is vital to ease the transformation process to foster growth and acceptance among industry partners as well as prepare for any unseen hurdles along the way. The work presented in this thesis focuses on designing and operating commercial vehicle fleets, introducing a novel fleet management system (FMS) framework capable of providing energy efficient mobility solutions. The FMS uses a recommender system comprised of a Design Space Filter (DSF) module to provide a feasible set of powertrains from the vehicle configuration database and uses machine learning algorithms to estimate the energy consumption for a given drive cycle, ranking them on the basis of their freight energy efficiency metric and ultimately aiding in the fleet composition design process. Due to the usage of highly confidential data pertaining to vehicle behavior, operators and OEMs are not keen on sharing this data unless there are agreements and secure data-sharing procedures established. Aware of this data bottleneck, the FMS leverages federated learning technique to estimate vehicular performance attributes and provides inferences which can be utilized for analyzing fleet behavior and enhancing fleet operations. This is extended to learn the mobility dynamics of (open full item for complete abstract)

Committee: Qadeer Ahmed (Advisor); Parinaz Naghizadeh (Committee Member); Manfredi Villani (Other) Subjects: Artificial Intelligence; Automotive Engineering; Computer Engineering; Electrical Engineering; Sustainability; Transportation

Master of Computer Science (M.C.S.), University of Dayton, 2022, Computer Science

Reinforcement Learning (RL) is an area of machine learning that enables an agent to learn in an interactive environment by trial and error using feedback from its own actions and experiences. NetHack presents a challenging problem for RL. It has a very large action space and multimodal observation space while requiring an agent to be capable of planning hundreds of thousands of timesteps to achieve a difficult goal. MiniHack is presented by Facebook AI Research to provide a testbed to develop incremental solutions toward the monumental goal of completing an ascension in NetHack. It presents a powerful framework for designing RL environments in procedurally generated worlds. Toward success in MiniHack, this thesis describes a method for masking actions to reduce the action space of agents. This thesis shows that masking actions can provide an effective means to artificially reduce the action space of any agent. Reducing the action space has been shown to increase the sample efficiency of agents in environments with large action spaces to few relevant actions.

Committee: Tam Nguyen (Advisor); Zhongmei Yao (Committee Member); James Buckley (Committee Member) Subjects: Computer Engineering; Computer Science

Doctor of Philosophy (Ph.D.), University of Dayton, 2021, Electrical Engineering

Deep Neural Networks (DNNs) are widely used in various application domains and achieve remarkable results. However, DNNs require a large number of computations for both the inference and training phases. Hardware accelerators are designed and implemented to compute DNN models efficiently. Many accelerators have been proposed for DNN inference, while only a limited set of DNN training accelerators has been proposed. Almost all of these accelerators are highly custom-designed and limited in the types of networks they can process. This dissertation focuses on designing novel architectures and tools for efficient training of deep neural networks, particularly for edge applications. We proposed several novel architectures and a design space exploration tool. Our proposed architecture can be used for efficient processing of DNNs, and the design space exploration model could help DNN architects explore the design space of DNN architecture design for both inference and training and help home in on the optimal architecture in different hardware constraints in applications. The first area of contribution in this dissertation is the design of Socrates-D-1, a digital multicore on-chip learning architecture for deep neural networks. This processing unit design demonstrates the capability to process the training phase of DNNs efficiently. A statically time-multiplexed routing mechanism and a co-designed mapping method are also introduced to improve overall throughput and energy efficiency. The experimental results show 6.8 to 22.3 times speedup and more than a thousand times energy efficiency over a GPGPU. The proposed architecture is also compared with several DNN training accelerators and achieves the best energy and area efficiencies. The second area of contribution in this dissertation is the design of Socrates-D-2, which is an enhanced version of Socrates-D-1. This architecture presents a novel neural processing unit design. A dual-ported eDRAM memory replaces the (open full item for complete abstract)

Committee: Tarek Taha (Committee Chair); Muhammad Usman (Committee Member); Vijayan Asari (Committee Member); Eric Balster (Committee Member) Subjects: Artificial Intelligence; Computer Engineering; Electrical Engineering

Master of Science, The Ohio State University, 2020, Mechanical Engineering

With the on-going electrification and data-intelligence trends in logistics industries, enabled by the advances in powertrain electrification, and connected and autonomous vehicle technologies, the traditional ways vehicles are designed by engineering experience and sales data are to be updated with a design for operation notion that relies intensively on operational data collection and large scale simulations. In this work, this design for operation notion is revisited with a specific combination of optimization and control techniques that promises accurate results with relatively fast computational time. The specific application that is explored here is a Class 6 pick-up and delivery truck that is limited to a given driving mission. A Gaussian Process (GP) based statistical learning approach is used to refine the search for the most accurate, optimal designs. Five hybrid powertrain architectures are explored, and a set of Pareto-optimal designs are found for a specific driving mission that represents the variations in a hypothetical operational scenario. A cross-architecture performance and cost comparison is performed and the selected architecture is developed further in the form of a forward simulator with a dedicated ECMS controller. In the end, a traffic-in-the-loop simulation is performed by integrating the selected powertrain architecture with a SUMO traffic simulator to evaluate the performance of the developed controller against varying driving conditions.

Committee: Giorgio Rizzoni (Advisor); Qadeer Ahmed (Committee Member) Subjects: Automotive Engineering; Engineering; Mechanical Engineering; Sustainability; Systems Design; Transportation

PhD, University of Cincinnati, 2004, Engineering : Computer Science and Engineering

With increasing complexity and size of VLSI systems, RTL can no longer be a viable design entry point. On the other hand, higher levels of abstraction takes the design description farther away from the physical characteristics of the system, making valuable, and necessary information unavailable to the synthesis process leading to problems in achieving design convergence. This work addresses three significant problems in providing a direct link to circuit and physical synthesis during high level design space exploration. (1) Developing methodologies for coupling circuit synthesis with high level synthesis design-space exploration for the design of high performance DSP designs, (2) Developing algorithms to couple high level synthesis with physical synthesis by performing incremental placement during high level synthesis design-space exploration, (3) Developing algorithms to couple high level synthesis and physical synthesis for vertically integrated 3D systems by performing simultaneous scheduling, binding and layer assignment for resources; and finding the best possible methodology for the performance optimization in terms of interconnect lengths in the critical path and inter-layer vias. Unlike previous research efforts that concentrate on obtaining estimates, our work aims at directly coupling high level synthesis decisions with circuit and layout synthesis. The proposed approaches allow us to examine larger design spaces to synthesize better designs, which would otherwise be pruned by a top-down synthesis flow.To leverage circuit level optimizations during high level design space exploration, we propose a methodology for performing on-demand resource topology modification using partial evaluation for constant operands during synthesis of application specific DSP circuits. We also propose a methodology to perform on-demand resizing of resources for the generation of constraint satisfying RTL at the end of behavioral synthesis. In order to integrate physical synthe (open full item for complete abstract)

Committee: Dr. Ranga Vemuri (Advisor) Subjects: Computer Science