Doctor of Philosophy, The Ohio State University, 2015, Electrical and Computer Engineering

With the continued growth of mobile communications, large portions of the RF spectrum are being utilized for a variety of wireless applications. For next-generation systems to adapt to this crowded and fluctuating wireless environment, future radio hardware must be capable of flexible and reconfigurable operation. Key to this endeavor is the development of high-performance digital-to-analog converters which can directly synthesize RF signals, bypassing the need for analog up-conversion and other RF processing by pushing functionality into the digital domain. In this work, a multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is developed for direct digital-to-RF synthesis. The proposed architecture uses only a single clock frequency (fS) for RF generation and includes a reconfigurable ΔΣ modulator (DSM) that operates in band-pass (BP) and high-pass (HP) modes to synthesize signals around fS=4, fS=2, or 3fs=4. Analog interleaving via two 3-bit DACs is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM, increasing the SNR, and easing filtering requirements. After a theoretical discussion, the proposed architecture is demonstrated by an initial prototype implemented in a 130 nm SiGe BiCMOS process and operating at fS = 2GHz. The design realizes a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50MHz bandwidth, and an in-band SFDR of 58.5 dB. In a second revision, an on-chip 14-bit DSM is included, implemented as an array of pipelined 1-bit pipelined subtracters to generate 3-bit, fS-rate input data. The second prototype also utilizes on-chip amplitude and timing calibration along with a CML data path to improve DAC speed, linearity, and SNR. Measurements at fS = 2GHz yield a 76.2 dB SIRR, 76.2 dB SFDR over a 100MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR and -66.4 dBc LTE ACLR. To enable the high-speed data input required by the RF-DAC, a fully integrated, AC coupled pul (open full item for complete abstract)

Committee: Khalil Waleed (Advisor); Roblin Patrick (Committee Member); Bibyk Steven (Committee Member) Subjects: Electrical Engineering; Engineering

MS, University of Cincinnati, 2023, Engineering and Applied Science: Chemical Engineering

In this study, we focused on improving the stability and energy efficiency of silica-supported amine. Polyethylenimine (PEI)-impregnated mesocellular siliceous foam (MCF) was synthesized and characterized. Adsorption performances in TGA showed that PEI/MCF can capture CO2 gas in both post-combustion conditions and ambient air. However, PEI/MCF showed limited stability against thermal and oxidative degradations. To overcome these drawbacks, 1,2 epoxy butane (EB) modification was introduced, and the performances of the EB-modified PEI/MCF sorbents were studied. The capacity measurement performed using thermogravimetric analyzer (TGA) showed that EB modification will lower the CO2 adsorption capacity and optimum temperature under both 15% and 400 ppm CO2. Cyclic test with desorption in 100% CO2 at 120 °C showed that EB-PEI can be fully regenerated without significant degradation and possess higher working capacity than unmodified PEI after several adsorption-desorption cycles. When cyclic test was performed in 400 ppm CO2/air, oxygen slightly negatively impacted on the stability. To study the oxidative degradation on EB modified PEI, accelerated oxygen aging under 100% O2 gas at 100 °C was applied, and the DRIFT spectra of O2¬ degraded sorbents was recorded with time. A new peak at 1,670 cm-1 was observed in oxygen degraded sorbent, and with an increase in EB modification ratio, the intensity of the peak decreased. The CO2 adsorption performance of the sorbent also improved with an increase in EB modification ratio. Heat of desorption measurement also showed decreasing regeneration energy and temperature with an increase in EB ratio.

Committee: Joo-Youp Lee Ph.D. (Committee Chair); Jingjie Wu Ph.D. (Committee Member); Peter Panagiotis Smirniotis Ph.D. (Committee Member) Subjects: Chemical Engineering

Doctor of Philosophy, Case Western Reserve University, 2023, Chemical Engineering

The goal of this PhD thesis is to develop materials that incorporate functionalized ionic liquids (ILs) and deep eutectic solvents (DESs) for CO2 removal from low CO2 concentration environments such as cabin air in spacecrafts and International Space Station, ISS, (< 5000 ppm of CO2). CO2 removal from such environments, especially in microgravity, requires certain considerations in material development such as light weight, small footprint, and long-life to enable sustainability in space which is a goal of the Artemis Program of the United States National Aeronautics and Space Administration (NASA). Current carbon dioxide removal assembly (CDRA) used by NASA utilizes porous solid sorbents called zeolites. Zeolites, similar to other solid sorbents based on metal organic frameworks, adsorb CO2 upon contact with air and release it upon increase in temperature (e.g., 350 °C). This process, referred as thermal-swing, is energy intensive and the repeated adsorption-desorption cycle creates fracture in the solid sorbent, thus resulting in dusting issue that damages downstream equipment in spacecraft and ISS. Therefore, there is a need of alternative materials that are selective to CO2, benign, lightweight, durable, and that require minimal energy to regenerate. ILs and DESs are of interest since they have tunable properties, and they are regarded as stable and ‘green' solvents. However, handling of liquids in microgravity is a challenge. Therefore, liquids require structural frameworks in order to be utilized in space applications. In this thesis, we demonstrate the design of functionalized ILs and DESs as environmentally benign energy-saving CO2 capture sorbents. These sorbents are immobilized in two different structural supports: polymeric capsules and membranes. Encapsulation of the selective ILs and DESs not only enable their handling in microgravity, it also provides large surface area for CO2 absorption. The liquid capsules can be used in the packed-bed CO2 scrubbi (open full item for complete abstract)

Committee: Burcu Gurkan (Committee Chair); Christine Duval (Committee Member); Donald Feke (Committee Member); Huichun (Judy) Zhang (Committee Member) Subjects: Chemical Engineering

Master of Science, The Ohio State University, 2022, Electrical and Computer Engineering

Next-generation hybrid pixel detectors aim to achieve timing resolutions on the order of 100 ps. Of primary concern is the analog front-end, composed of preamplifier and discriminator, which introduce significant timing uncertainty to the sensor charge signal they transduce. This work presents an on-chip test circuit capable of characterizing the jitter of pixel detector analog front-ends constructed in 28 nm bulk CMOS. The test system injects an artificial sensor charge pulse at the input of the device-under-test and then measures the output timing variation with a time-to-digital converter. The measurement circuit can inject charge quantities up to 24,000 electrons, with a timing precision of 10.1 ps RMS, a maximum differential non-linearity of 0.25 LSB, and a dynamic range of 64 ns.

Committee: Wladimiro Villarroel (Advisor); Maurice Garcia-Sciveres (Committee Member); Ayman Fayed (Committee Member); Tawfiq Musah (Committee Member) Subjects: Electrical Engineering

Master of Science in Electrical Engineering (MSEE), Wright State University, 2019, Electrical Engineering

Many wired and wireless communication systems require high-speed and high-performance data converters. These data converters act as bridge between digital signal processing blocks and power amplifiers. However, these data converters have been the bottleneck in the communication systems. This thesis presents the design of a 10-bit C2C digital to analog converter (DAC) for high resolution, wide bandwidth and low power consumption applications. The DAC is implemented in CMOS 65nm technology. The SFDR of this C2C DAC is 71.95dB at 500MHz input frequency and consumes 88.14µW of power with ENOB as 11.65 with 1.0GHz sample frequency with 0.31LSB of INL and 0.5LSB of DNL. A 10-bit SAR ADC is designed using this proposed C2C DAC with 427.4µW of power consumption at 1.0V voltage supply.

Committee: Saiyu Ren Ph.D. (Advisor); Ray Siferd Ph.D. (Committee Member); Marian K. Kazimierczuk Ph.D. (Committee Member) Subjects: Electrical Engineering

Ph.D., Antioch University, 2018, Leadership and Change

Multiple voices from educational and professional arenas have called for change in the way in which public relations undergraduates are prepared to navigate complex communication challenges in the 21st century. Some scholars have advanced leadership as a way to address this change, identifying the undergraduate public relations curriculum as the ideal place to introduce future practitioners to leadership as a way to better prepare them to initiate and participate in positive social change in complex contexts. However, scholars have neither made in-depth connections with leadership theory and practice, nor provided a framework for designing a curriculum for incorporating leadership into public relations undergraduate programs. The purpose of this research was to examine the practice of inclusive leadership and communication in an exemplary organization in order to answer the question: What would an undergraduate public relations leadership (PRL) curriculum look like? Portraiture was used to uncover and illustrate the key ways in which inclusive leadership and communication manifest at a successful Chicago-based interactive technology firm. Findings support the idea that an inclusive leadership and communication culture is created through direction, alignment, and commitment (DAC). Furthermore, the research provides evidence that inclusive leadership and communication skills can be developed through practice and support. An analysis of sample public relations undergraduate programs was used in conjunction with research findings to bridge the gap between inclusive leadership development and public relations undergraduate education. A public relations leadership (PRL) curriculum was created to help public relations undergraduate students better develop leadership, communication, and relational skills. This dissertation is available in open access at AURA: Antioch University Repository and Archive, http://aura.antioch.edu/ and Ohiolink ETD Center, https://etd.ohiolink.ed (open full item for complete abstract)

Committee: Lize A. E. Booysen DBL (Committee Chair); Laurien Alexandre PhD (Committee Member); Pete Smudde PhD, APR (Committee Member); Dean Mundy PhD (Other) Subjects: Communication; Curriculum Development; Education; Educational Leadership; Higher Education; Marketing; Mass Communications; Personal Relationships

PHD, Kent State University, 2016, College of Arts and Sciences / Department of Computer Science

Proper access control is one of the most important issues in computer security. It consists of securing a system in the form of availability, confidentiality, and integrity. Integrity is about making sure that only proper modifications take place. Some integrity models are static in nature, which may limit their capabilities for better protection of a system. In some cases like in the collaborative authoring systems (e.g. Wikipedia), such static models are not desired because there is a need for continuous evaluations of posted work. This motivated us to present a dynamic integrity model based on a metric we call the modification factor to evaluate whether the integrity level should be changed up or down. Furthermore, our dynamic model allows us to establish a level of trustworthiness that an entity has as a source or destination of information.

Committee: Austin Melton (Advisor); Johnnie Baker (Committee Member); Michael Rothstein (Committee Member); Kambiz Ghazinour Naini (Committee Member); Stephen Gagola (Committee Member); Alan Brandyberry (Other) Subjects: Computer Science

Master of Science in Engineering (MSEgr), Wright State University, 2015, Electrical Engineering

Digital analog converters bridge the gap between digital signal processing chips, and power amplifiers that transmit analog signals. Communications systems require ever increasing bandwidth, however data converters are typically the bottleneck in these systems. This thesis presents the design of a high speed current steering DAC using CMOS 90 nm technology. The resolution of the converter is 10 bits, segmented into 6 thermometer encoded MSB current cells, and 4 binary weighted LSB current cells. Each of the sub-components, such as the binary-thermometer encoder, digital latch, current cell, reconstruction filter, are discussed in detail. The current cells were designed with transistor matching, and output impedance effects in mind to achieve high performance. The DNL of the converter was measured to be 0.02 LSB, while the INL is 0.29 LSB. With a clock frequency of 1.2 GHz, the SFDR was measured to be 72.07 dB with an input of 596.48 MHz.

Committee: Saiyu Ren Ph.D. (Advisor); Raymond Siferd Ph.D. (Committee Member); John Emmert Ph.D. (Committee Member) Subjects: Electrical Engineering

Master of Science in Engineering, University of Akron, 2015, Electrical Engineering

This work describes an area efficient 10-bit time mode hybrid DAC with current settling error compensation. The proposed 10-bit hybrid DAC is realized using a current steering DAC for the lower bits conversion and a time mode DAC for the upper bits conversion. The time mode DAC consist of a single capacitor, amplifier, current mirror and several control switches which occupies less area than other DAC architectures. The time mode DAC current settling error occurs because of the capacitor current not immediately responding to the control pulse, which further decreases the DAC output voltage. A compensation pulse corresponding to the DAC error voltage is generated and is added to the control pulse to compensate the DAC output voltage error caused by improper current settling. In addition, the time mode DAC current settling error compensation does not critically increase the area. The proposed DAC is realized using 0.35µm CMOS technology with estimated core area of 0.00463mm2, which is less than most of the existing 10-bit DACs published in the literature. The maximum DNL and INL with error compensation showed 0.5LSB and -0.6LSB, respectively.

Committee: Kye Shin-Lee (Advisor) Subjects: Electrical Engineering

Master of Science in Engineering (MSEgr), Wright State University, 2007, Electrical Engineering

Poling, Brian S. M.S. Egr., Department of Electrical Engineering, Wright State University, 2007. On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In Self-Test. Built-In Self-Test (BIST) is a method of designing and creating an electronic chip or an electronic system that can self test for correct functionality and ensure no manufacturing defects. The reason for analog BIST is the testing of analog parts of analog and mixed-signal ICs is a costly process that traditionally requires the use of expensive high-end automatic test equipment. Due to the nature of the testing and length of the testing process, an efficient analog BIST scheme is in high demand for the ever increasing complexity of analog and mixed-signal circuits. This thesis presents a BIST scheme for generation and response waveform extraction that allows the detection of a faulty circuit design. Along with the detection, an approach to test high speed analog and mixed-signal circuits with test signals upwards of 1GHz is presented. A practical application is to test analog or mixed-signal IC that has a wide bandwidth ADC in its front-end. The BIST scheme includes a method to store the test signal and generate it for the circuit to be tested along with a way to extract the response test signal from multiple test points and allow fault detection. Along with this research, a stepping stone is implemented for analog modeling using MATLAB for accuracy and speed of circuit simulations. The problems associated with the BIST scheme and analog modeling is discussed, along with recommendations.

Committee: Henry Chen (Advisor) Subjects:

Master of Science in Engineering (MSEgr), Wright State University, 2006, Electrical Engineering

For the process of converting low-power digital signals into their high-power analog counterparts, the functions of digital-to-analog conversion (at low power) and analog power amplification are separately implemented. This thesis proposes a new “STAC-DAC” circuit topology which directly realizes high-power analog output from low-power digital input signals. The ability to achieve a “direct from digital” high-power analog output in a single high-efficient, low-distortion design has significant potential in audio reproduction, and flexible signal generation applications. In this thesis, the “STAC-DAC” is described and its implementation via MATLAB and LTSpice is discussed. The results of simulations are used to prove the concept of the design. The 16-bit design features a high-power output of 100 watts or more at an efficiency of 93%. The design is optimized to feature low total harmonic distortion (THD) of 0.055% for a 1 kHz signal at 100 watts into an 8 Ω load and low phase distortion of less than 10° for a 20 kHz signal and only 1° at 1 kHz. The “STAC-DAC” design is applicable to any design which requires a high-power analog output that is controlled by a logic level digital input. The results validated that the “STAC-DAC” can produce low-level THD figures over the audio frequency range. If very low THD figures are not necessary, high-power analog operation can be achieved into the hundreds of kilohertz while maintaining high efficiency. These results show that the power “STAC-DAC” is capable of simultaneously achieving the highly efficient circuitry associated with digital-to-analog converters with the low harmonic and phase distortion requirements associated with high fidelity analog audio amplifiers.

Committee: Marian Kazimierczuk (Advisor) Subjects:

MS, University of Cincinnati, 2010, Engineering : Electrical Engineering

For digital mobile phone services in Canada, Mexico and the United States, Personal Communications Service (PCS) is one of the most popular standards, and its downlink frequency band is centered at 1.96GHz with 60MHz bandwidth. This research presents a microcontroller AT89c5131 configured active analog phase shifter at 1.96GHz with phase-shifting range of 90°. The phase shifter can be applied in cellular base station downlink circuits, and the concept could be extended to radar and smart antenna applications. The vector addition phase shifter has the following advantages: using microcontroller (MCU) increases the flexibility of control circuits and provides possibility to extend the phase shifter to a phased array antennas system smoothly; applying algorithm to compensate the amplifier's gain-versus-control-voltage non-linear characteristics results in continuous phase shifting with a small RMS phase error of 1.3° constant gain (|S21|>1) increases transmission power efficiency.

Committee: Altan Ferendeci PhD (Committee Chair); Peter Kosel PhD (Committee Member); Joseph Thomas Boyd PhD (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, Case Western Reserve University, 2009, EECS - Electrical Engineering

Chemical signals manifested by messenger molecules are omnipresent in the life sciences. The ability to generate such chemical and biological signals artificially in microscale will be an enabling factor in probing, understanding, controlling and regulating complex biological systems. Microfluidics with many advantages such as consumption of small volume of sample and reagents, having a low cost, offer faster response and have a small footprint. In this dissertation, for the first time, the design, fabrication and testing of different architectures of microfluidic chemical concentration signal generators inspired by Digital to Analog Converters (DAC) are thoroughly studied. These chemical concentration signals generators are often called Concentration Digital to Analog Converter or C-DAC. The main idea is to generate binary weighted streams of chemical concentration signals and then select, direct and intermix those streams of concentration signals to the output based the value of digital input code generated by a computer program. Three different architectures which are developed in this research are based dilution networks, Pulse Code Modulators (PCM) and Multi-Plug Modulators (MPM). Modeling and simulation of microfluidic devices with hundreds of components at system level using conventional computational fluid dynamic (CFD) methods is very challenging and often impractical. A new lumped model which is inclusive of dispersion and convection is developed based on one-dimensional discretization of the convection-diffusion equation. The model which is implemented using Verilog-AMS is capable of tracking the transport of solvent and solute inside a microfluidic system using four dual-branch lumped nodal quantities of solvent pressure, solvent flow rate, solute concentration and solute current. The simulation results of Lab On Chip SIMulator tool (or simply LOCSIM) are in a very good agreements with the experimental results. The chemical concentration signal generator (open full item for complete abstract)

Committee: Carlos Mastrangelo PhD (Advisor); Steven Garverick PhD (Committee Member); Chris Zorman PhD (Committee Member); Chris Dealwis PhD (Committee Member) Subjects: Electrical Engineering

Master of Science, University of Akron, 2012, Electrical Engineering

In this thesis, a 10-bit dual plate sampling capacitor DAC with reduced offset internal reference voltage generation is proposed. Instead of using the conventional two element switched capacitor circuit that consists of the charge sampling and summing capacitor, the proposed scheme performs the identical operation using a single capacitor without affecting the conversion speed. As a result, the capacitor area can be considerably reduced compared to conventional capacitive DACs, which eventually leads to power saving due to amplifier effective load reduction and feedback factor improvement. The auto-zero internal reference voltage generator replaces the resistive ladder voltage divider with two unit capacitors, reference amplifiers, and several switches which further reduces the area of the DAC. In addition, the effect of major non-idealities including reference voltage mismatch, capacitor mismatch, and parasitic capacitance are analyzed. The proposed DAC is implemented using CMOS 0.35µm technology with core size of 0.11mm2. The maximum INL and DNL measured in a fabricated circuit were 0.67 LSB and 0.33 LSB, respectively.

Committee: Kye-Shin Lee Dr. (Advisor); Joan Carletta Dr. (Committee Member); Robert Veillette Dr. (Committee Member) Subjects: Electrical Engineering; Engineering

Doctor of Philosophy, University of Akron, 2007, Polymer Science

One of the biggest challenges in solid state physics today is understanding the nature of the glass transition. Dynamic studies are critical in solving some of the problems in the field. Until recently, investigations of dynamics in glass formers were mostly carried out as a function of temperature. However, with the advancements in experimental techniques and methods, the interest towards using pressure as an additional experimental variable increased. The advantages of pressure over temperature are two-fold: First, it only alters the density of the system, whereas temperature changes both the thermal energy and the density, and secondly, one can achieve significant density changes (~20%) with pressure, whereas temperature creates smaller density changes (~5%). These advantages let researchers make direct comparisons of the results with glass transition models (i.e. free volume ideas). The dynamics in the frequency range between 1 GHz and 5 THz (fast dynamics), are thought to have a crucial role. Crystals in this frequency range have a Debye-like density of vibrational states. Glasses, however, have two extra contributions when compared to crystalline structures: (i) an anharmonic relaxation-like contribution that appears as a quasielastic scattering (QES) and (ii) a harmonic vibrational contribution, which shows up as the boson peak (BP) in light and neutron scattering spectra. It has also been shown experimentally that fast dynamics in glasses are strongly correlated with the temperature dependence of structural relaxation.In this dissertation the influence of pressure on fast dynamics in polyisobutylene, polyisoprene and low molecular weight polystyrene is investigated using inelastic light, neutron and X-ray scattering techniques. The results are compared to the predictions of the existing models.The results for all polymers studied showed that the boson peak shifts more strongly than sound modes, suggesting that the variations cannot be fully described by the (open full item for complete abstract)

Committee: Alexei Sokolov (Advisor) Subjects: