Master of Science, The Ohio State University, 2020, Electrical and Computer Engineering

Baud rate clock and data recovery circuits are critical to high speed serial links since these require only one sample per data period thereby requiring low speed samplers and comparators. This work models and discusses the backend of one particular Baud rate CDR – Mueller Muller, and analyses some of the building blocks of the CDR – Phase Detector, Phase Interpolator and the Quadrature Phase Generator. Firstly, a PAM-4 Quadrature Phase Detector operating at 80Gb/s is discussed. The challenges associated with designing a Mueller-Muller PD for an asymmetric channel are discussed and one way to resolve this issue is proposed. Then the underlying digital blocks that make up the Phase detector are expanded upon. Secondly, a 64-step digitally controlled Phase Interpolator running at 16GHz clock rate is analyzed and its design challenges with regards to achieving linearity and ensuring duty cycle fidelity are explored. Finally, a Quadrature Phase Generator with digital delay control is analyzed. It is modeled at 16GHz clock rate and the range/resolution problem and its impact on clock jitter is explored.

Committee: Tawfiq Musah (Advisor); Ayman Fayed (Committee Member) Subjects: Electrical Engineering