Master of Science, The Ohio State University, 2022, Electrical and Computer Engineering

Next-generation hybrid pixel detectors aim to achieve timing resolutions on the order of 100 ps. Of primary concern is the analog front-end, composed of preamplifier and discriminator, which introduce significant timing uncertainty to the sensor charge signal they transduce. This work presents an on-chip test circuit capable of characterizing the jitter of pixel detector analog front-ends constructed in 28 nm bulk CMOS. The test system injects an artificial sensor charge pulse at the input of the device-under-test and then measures the output timing variation with a time-to-digital converter. The measurement circuit can inject charge quantities up to 24,000 electrons, with a timing precision of 10.1 ps RMS, a maximum differential non-linearity of 0.25 LSB, and a dynamic range of 64 ns.

Committee: Wladimiro Villarroel (Advisor); Maurice Garcia-Sciveres (Committee Member); Ayman Fayed (Committee Member); Tawfiq Musah (Committee Member) Subjects: Electrical Engineering

Master of Sciences (Engineering), Case Western Reserve University, 2020, EECS - Electrical Engineering

Ground-penetrating radar (GPR) is a widely popular sensing method that provides subsurface images in a non-destructive manner. The first part of this work presents a multistatic GPR for vehicle-mounted roadway and utility monitoring applications that employs three methods to improve its performance compared to the state-of-the-art. First of all, the system illuminates the subsurface with pseudo-random codes (m-sequences) that have near-ideal autocorrelation properties. Therefore, the received signal can be matched-filtered to provide pulse compression, which improves both range-resolution and depth of scan compared to traditional impulse-based GPRs. Second of all, the system uses a highly-digital transmit and receive architecture based on direct FPGA-based transmit pulse generation and direct radio frequency (RF) sampling. Last but not least, the analog front-end uses an 8x8 multistatic antenna array design with broadband antipodal Vivaldi elements to provide spatial diversity, leading to improved object localization and reduced drift between scans. Experimental results from indoor and outdoor test-beds confirm the functionality of the proposed GPR system. The second part of this work proposes a proof-of-concept design of a multi-channel broadband low-noise analog front-end (AFE) for multistatic GPR receivers. This custom integrated circuit (IC) design employs the standard TSMC180 CMOS process. The IC includes four amplifier channels; each channel consists of a broadband low-noise amplifier (LNA) employing noise-canceling techniques, a gm-cell-based variable gain amplifier (VGA), and a voltage buffer. This combination allows the IC to achieve low noise figure (NF) and high linearity performance, thus improving the effective resolution and scan depth of the GPR. Measurement results confirm the functionality of the proposed custom multi-channel AFE IC.

Committee: Soumyajit Mandal (Committee Chair); Kenneth Loparo (Committee Member); Hossein Miri Lavasani (Committee Member) Subjects: Electrical Engineering

PhD, University of Cincinnati, 2018, Engineering and Applied Science: Electrical Engineering

The future of disease diagnostics and health care wearables lies in the development of low-cost sensors and devices that can detect minute traces of pathogens or antigens from body fluids. These devices will allow patients to run point of care diagnostics tests, thereby saving time and cost of running clinical tests and ultimately can provide early stage disease diagnosis and enable physicians to provide better-personalized treatment. There have been developments that focus on integrating multiple different tests into a single device that measures analytes from biofluids. Detection of glucose together with some single ions in a single device and test is the current attractive research advancement. Electrochemistry Impedance Spectroscopy (EIS) is widely popular in the medical field where it is used to analyze biological materials as well as characterization of body fluids. It is a complex technique requiring expensive equipment that is also bulky making it difficult to integrate into small form-factor systems that are handheld, wearable and intended for use in point of care testing. This research work focused on developing a proof of concept prototype system with a flexible architecture that can be used for testing multiple sensors using EIS electroanalytical technique. The system is based on an embedded system design to be factored to achieve small valuation time for results along with being compact and portable enough to be used outside laboratory bench setting. The prototype successfully calculates the magnitude and phase of the impedance responses multiple electrochemical cells. The device transmits test data wirelessly to a personal computer or tablet which works together with an analysis and control display.

Committee: Fred Beyette Ph.D. (Committee Chair); Jason Heikenfeld Ph.D. (Committee Member); Carla Purdy Ph.D. (Committee Member); Ryan White Ph.D. (Committee Member); Philip Wilsey Ph.D. (Committee Member) Subjects: Electrical Engineering

Master of Science in Engineering (MSEgr), Wright State University, 2015, Electrical Engineering

In order to accurately reconstruct signal waveform a signal must be sampled at least twice as fast as the bandwidth of the signal. Ultra Wideband (UWB) signals have extraordinary potential for high information transmission while a central focus of wireless has been the mobile communication. It is an emerging area that involves development of RF sensing and spectral applications over multiple GHz bandwidths. Even though our technology is improving, it is very challenging to build ADC's that are compatible and keep up with the growth of ultra-wideband range. Compressive sensing does “sampling” and “compressing” at the same time and exploits the sparsity for commensurate power saving by enabling sub-Nyquist under-sampling acquisition. The main idea behind compressive sensing is to recover specific signals from very few samples as compared to conventional Nyquist samples. In this thesis, a compressive sensing front-end (CSFE) is designed and analyzed to mitigate sampling approach limitations of the architecture in a CMOS process. CSFE has four main components: pseudo random sequence generator (PBRS), multiplier, integrator, and ADC. The PBRS (implemented by a Gold code generator) and the multiplier are designed in Cadence Spectre using TSMC 180nm technology. The integrator and the 10-bit ADC are designed and verified using both Verilog-A and Matlab. Using 4 GHz PBRS and 800 MHz under sampling ADC, the CSFE design can detect signal frequency up to 2 GHz after applying the Orthogonal Matching Pursuit algorithm to reconstruct the under sampling ADC data.

Committee: Henry Chen Ph.D. (Committee Chair); Marian Kazimierczuk Ph.D. (Committee Member); Jiafeng Xie Ph.D. (Committee Member) Subjects: Electrical Engineering

Doctor of Philosophy, The Ohio State University, 2006, Electrical Engineering

This dissertation presents a single mode direct conversion receiver architecture and the corresponding CMOS front-end for low power consumption, small form factor, low noise figure and high linearity wide band code division multiple access (WCDMA) receiver in a TSMC 0.18-µm process. The front end comprises a novel differential low noise amplifier (LNA) and a novel down-conversion mixer. One of the major advantages of differential LNAs is that they are much less susceptible to common mode injected noise such as substrate noise. This is a very important issue in cases where the LNA is to be integrated with digital circuits that may generate in-band noise and interference. Also the leakage problem, where signals such as the LO couples to the antenna through the LNA input port, may be greatly alleviated by use of differential circuits. The proposed LNA has dual gain mode; low gain mode (LGM) and high gain mode (HGM). The variable gain LNA reduces the dynamic range requirement for the succeeding stages and also reduces the required gain of the baseband filter (BBF). The proposed down-conversion I/Q mixer structure is chosen to be a differential double balanced mixer for its inherited insensitivity to LO-IF isolation. It also suppresses common-mode substrate noise and interference. Also, this proposed topology reduces the power by up to 50 percent compared to a conventional down-conversion mixer. The undesired bondwire and package parasitics such as capacitors, inductors, and resistors are taken into account during the schematic design and layout. These undesired parasitics may affect the gain response and input impedance matching of the LNA and the gain and phase mismatch of the mixer. The proposed RF front-end is simulated with the Cadence SpectreRF simulator. Although it shows the degradation of the gain and the input impedance to some extent, the proposed front-end shows high linearity, low noise figure, very low corner frequency in the flicker noise, negligible gain (open full item for complete abstract)

Committee: Joanne DeGroat (Advisor) Subjects: