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Low-Power, Low-Cost, & High-Performance Digital Designs: Multi-bit Signed Multiplier design using 32nm CMOS Technology

Boppana, N V Vijaya Krishna
http://orcid.org/0000-0001-7331-317X
http://rave.ohiolink.edu/etdc/view?acc_num=wright1661329648872332

Abstract Details

2022, Doctor of Philosophy (PhD), Wright State University, Electrical Engineering.
Binary multipliers are ubiquitous in digital hardware. Digital multipliers along with the adders play a major role in computing, communicating, and controlling devices. Multipliers are used majorly in the areas of digital signal and image processing, central processing unit (CPU) of the computers, high-performance and parallel scientific computing, machine learning, physical layer design of the communication equipment, etc. The predominant presence and increasing demand for low-power, low-cost, and high-performance digital hardware led to this work of developing optimized multiplier designs. Two optimized designs are proposed in this work. One is an optimized 8 x 8 Booth multiplier architecture which is implemented using 32nm CMOS technology. Synthesis (pre-layout) and post-layout results show that the delay is reduced by 24.7% and 25.6% respectively, the area is reduced by 5.5% and 15% respectively, the power consumption is reduced by 21.5% and 26.6% respectively, and the area-delay-product is reduced by 28.8% and 36.8% respectively when compared to the performance results obtained for the state-of-the-art 8 x 8 Booth multiplier designed using 32nm CMOS technology with 1.05 V supply voltage at 500 MHz input frequency. Another is a novel radix-8 structure with 3-bit grouping to reduce the number of partial products along with the effective partial product reduction schemes for 8 x 8, 16 x 16, 32 x 32, and 64 x 64 signed multipliers. Comparing the performance results of the (synthesized, post-layout) designs of sizes 32 x 32, and 64 x 64 based on the simple novel radix-8 structure with the estimated performance measurements for the optimized Booth multiplier design presented in this work, reduction in delay by (2.64%, 0.47%) and (2.74%, 18.04%) respectively, and reduction in area-delay-product by (12.12%, -5.17%) and (17.82%, 12.91%) respectively can be observed. With the use of the higher radix structure, delay, area, and power consumption can be further reduced. Appropriate adder deployment, further exploring the optimized grouping or compression strategies, and applying more low-power design techniques such as power-gating, multi-Vt MOS transistor utilization, multi-VDD domain creation, etc., help, along with the higher radix structures, realizing the more efficient multiplier designs.
Saiyu Ren, Ph.D. (Advisor)
Raymond E. Siferd, Ph.D. (Committee Member)
Henry Chen, Ph.D. (Committee Member)
Marian K. Kazimierczuk, Ph.D. (Committee Member)
Yan Zhuang, Ph..D. (Committee Member)
Michael Saville, Ph.D., P.E. (Other)
Barry Milligan, Ph.D. (Other)
125 p.
Computer Engineering; Electrical Engineering
Digital Design; Digital Multiplier; Signed Multiplier; Low-power; Low-cost; High-performance; Modified Booth; Radix-8 structure; 8 x 8; 16 x 16; 32 x 32; 64 x 64; 32nm CMOS Technology; Synthesize; Placement & Route (PnR);

Recommended Citations

Citations

  • Boppana, N. V. V. K. (2022). Low-Power, Low-Cost, & High-Performance Digital Designs: Multi-bit Signed Multiplier design using 32nm CMOS Technology [Doctoral dissertation, Wright State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=wright1661329648872332

    APA Style (7th edition)

  • Boppana, N V Vijaya Krishna. Low-Power, Low-Cost, & High-Performance Digital Designs: Multi-bit Signed Multiplier design using 32nm CMOS Technology. 2022. Wright State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=wright1661329648872332.

    MLA Style (8th edition)

  • Boppana, N V Vijaya Krishna. "Low-Power, Low-Cost, & High-Performance Digital Designs: Multi-bit Signed Multiplier design using 32nm CMOS Technology." Doctoral dissertation, Wright State University, 2022. http://rave.ohiolink.edu/etdc/view?acc_num=wright1661329648872332

    Chicago Manual of Style (17th edition)

wright1661329648872332
271
© 2022, some rights reserved.Creative Commons License Low-Power, Low-Cost, & High-Performance Digital Designs: Multi-bit Signed Multiplier design using 32nm CMOS Technology by N V Vijaya Krishna Boppana is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by Wright State University and OhioLINK.