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Efficient Techniques for Logic Locking

Saxena, Nikhil
http://orcid.org/0000-0002-6240-4719
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1712916528262962

Abstract Details

2024, PhD, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
In the semiconductor industry, protecting Integrated Circuits (IC) throughout the IC supply chain has become a major concern. With the globalization of the design process, the increasing cost of fabrication, and the complex manufacturing process of ICs, Hardware security has become a prominent issue. Especially, the increasing cost of IC fabrication has forced design houses to depend on potentially untrusted foundries to fabricate their ICs. At every step of the IC supply chain, ICs have become vulnerable to several potential attacks, including reverse engineering, overproduction, counterfeiting, trojan insertion, and IP theft. Design-for-trust schemes have emerged in recent years to overcome these threats. In-depth research has been done on logic encryption, split manufacturing, and layout camouflaging to safeguard ICs against attacks at various stages of the supply chain. Among the most promising schemes are logic encryption and layout camouflaging, which can thwart potential attacks at multiple supply chain stages. To safeguard ICs at every stage of the supply chain, including the foundry, the testing facility, and the end user, this research aims to create new logic locking strategies. We suggest creating a novel “SRTLock” two-tier logic encryption technique to protect the IC from sensitivity analysis attacks. In order to safeguard ICs at various points along the IC supply chain, we also proposed the “ISPLock” hybrid internal state locking method. In order to make sure that the IC cannot be used without the proper key, this technique also offers a high average output corruption rate (OCR) for the protected circuit. To increase the overall security of ICs, logic locking and camouflaging are both used together. Additionally, a “Hybrid Shielding” technique using polymorphic gates has been developed to guarantee security at every stage of the IC supply chain. It uses dynamic camouflaging and logic locking to ensure high security and a high rate of OCR. These techniques limit the number of key inputs, account for the area overhead, and suggest sharing the key inputs among the polymorphic gates. The assessment of Power, Performance, and Area (PPA) overhead is integral in evaluating the effectiveness of proposed encryption methods. Notably, there exists a gap in existing literature regarding a standardized method for quantifying PPA overhead, particularly tailored to hybrid logic encryption techniques. This research addresses this gap by introducing a mathematical framework designed to estimate the approximate PPA associated with circuits encrypted through hybrid shielding methods. Our approach is a two-step process, establishing a systematic means of evaluating the impact of hybrid logic encryption on power consumption, performance metrics, and circuit area. The analysis of circuit characteristics plays a pivotal role in determining circuit performance in the context of OCR. This research analyses OCR across diverse synthetic circuit types. The study introduces two distinct methodologies for the selection of circuit nodes suitable for encryption and camouflage, both derived from thorough circuit characterization.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Sumeet Chaudhary, Ph.D. (Committee Member)
Mike Borowczak, Ph.D. (Committee Member)
John Emmert, Ph.D. (Committee Member)
147 p.
Electrical Engineering
Logic Encryption; Camouflaging; Output Corruption Rate; Hardware Security; PPA Overhead; IC Supply Chain

Recommended Citations

Citations

  • Saxena, N. (2024). Efficient Techniques for Logic Locking [Doctoral dissertation, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1712916528262962

    APA Style (7th edition)

  • Saxena, Nikhil. Efficient Techniques for Logic Locking. 2024. University of Cincinnati, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1712916528262962.

    MLA Style (8th edition)

  • Saxena, Nikhil. "Efficient Techniques for Logic Locking." Doctoral dissertation, University of Cincinnati, 2024. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1712916528262962

    Chicago Manual of Style (17th edition)

ucin1712916528262962
231
© 2024, some rights reserved.Creative Commons License Efficient Techniques for Logic Locking by Nikhil Saxena is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by University of Cincinnati and OhioLINK.
Release 3.2.12