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An Abstract Approach To FPGA LUT Bitstream Reverse Engineering

Stowasser, Heiko
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1659529817834067

Abstract Details

2022, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
Field Programmable Gate Arrays (FPGAs) are integrated circuits designed so they can be reprogrammed to implement any logic circuit. FPGAs are used in critical systems like military radar and wireless communication infrastructure, making FPGA security critical. One major threat to the security of FPGAs are Trojans. Trojans are malicious modifications made to a circuit at any point in the design process. The reprogrammable nature of FPGAs makes them doubly vulnerable to Trojans because even if the physical chip is secure Trojans can still be inserted by compromising the bitstream that programs the FPGA. These types of Trojans could be detected by analyzing the bitstreams of affected FPGAs. However, FPGA manufacturers do not publish the format of bitstreams, providing a layer of inherent obfuscation for attackers to exploit. Meaning that the format of an FPGA's bitstream must be reverse engineered before it is possible to analyze the bitstream for Trojans. Existing methodologies for reverse engineering FPGA bitstreams require expert knowledge of an FPGA's architecture and its associated toolchain. In this Thesis we demonstrate a methodology of reverse engineering FPGA Look-Up-Tables (LUTs), the fundamental component of FPGA reprogrammable logic. Our methodology uses generic VHDL, which allows it to be easily ported to different FPGAs with only basic knowledge of FPGA design flow.
John Emmert, Ph.D. (Committee Member)
Ranganadha Vemuri, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
48 p.
Computer Engineering
FPGA; Trojans; Reverse Engineering; Hardware Security; Bitstream

Recommended Citations

Citations

  • Stowasser, H. (2022). An Abstract Approach To FPGA LUT Bitstream Reverse Engineering [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1659529817834067

    APA Style (7th edition)

  • Stowasser, Heiko. An Abstract Approach To FPGA LUT Bitstream Reverse Engineering. 2022. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1659529817834067.

    MLA Style (8th edition)

  • Stowasser, Heiko. "An Abstract Approach To FPGA LUT Bitstream Reverse Engineering." Master's thesis, University of Cincinnati, 2022. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1659529817834067

    Chicago Manual of Style (17th edition)

ucin1659529817834067
1,084
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This open access ETD is published by University of Cincinnati and OhioLINK.