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Assertion-Based Monitors for Run-time Security Validation

Shankaranarayanan, Bharath
http://orcid.org/0000-0003-4777-927X
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1626356515627044

Abstract Details

2021, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
A modern hardware processor consists of many modules that are integrated into a System-on-Chip (SoC). Sensitive modules must be protected against malicious attacks. Most high-performance processing machines used in security assurance systems are produced and assembled abroad. With enough resources, an attacker could maliciously modify a general-purpose processor across many stages of the acquisition chain, from design and manufacturing to assembly and transport. These altered processors might figure out a way into high-security systems. Security validation is one method to ensure that a future attack can be thwarted before its manifestation. Pre-silicon verification involves verifying designs in a virtual environment with simulation, emulation, and formal verification methods at the design level. Assertion-based verification is a widely used formal verification technique. Assertions ensure functional correctness during the design and verification phases. To extend the assertion-based verification technique to functional testing during silicon bring-up requires the translation of these assertions into post-fabrication run-time security monitors is employed. A security monitor - translation of these pre-fab security assertions, when embedded with the Design Under Test (DUT) in the long run, proves helpful in observing security vulnerability. This thesis presents a compiler for post-fabrication monitoring of assertions, implemented based on System Verilog Assertions (SVA). The compiler's core purpose is to translate SVA into run-time Verilog monitors added to the DUT for post-silicon validation. The entire compiler has been developed using the Python and PLY Python Lex-Yacc framework. Monitors thus generated are verified for their ability to catch an error during run-time. We have checked the compiler's robustness by applying numerous tests in a systematic approach from basic to complex input assertions. We have also analyzed the monitors' performance to show that the method is scalable for large systems by applying it on two different SoC's.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
132 p.
Electrical Engineering
Assertion-Based Verification; System Verilog Assertions; Assertion-based Monitors; Security and Hardware Monitors

Recommended Citations

Citations

  • Shankaranarayanan, B. (2021). Assertion-Based Monitors for Run-time Security Validation [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1626356515627044

    APA Style (7th edition)

  • Shankaranarayanan, Bharath. Assertion-Based Monitors for Run-time Security Validation. 2021. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1626356515627044.

    MLA Style (8th edition)

  • Shankaranarayanan, Bharath. "Assertion-Based Monitors for Run-time Security Validation." Master's thesis, University of Cincinnati, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1626356515627044

    Chicago Manual of Style (17th edition)

ucin1626356515627044
74
© 2021, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.