Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


36447.pdf (4.36 MB)

ETD Abstract Container

Abstract Header

Heuristics for Signal Selection in Post-Silicon Validation

Tummala, Suprajaa
http://orcid.org/0000-0001-5542-7915
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573573253403988

Abstract Details

2019, MS, University of Cincinnati, Engineering and Applied Science: Computer Engineering.
As a result of the increasing design complexity, validating the designs at the pre-silicon design stage to capture all the bugs has become nearly impossible. Bugs escaped at pre-silicon verification are identified at the post-silicon validation stage making it an important step in the implementation flow of digital integrated circuits. Limited observability is the key challenge in post-silicon validation and can be improved by using an on-chip trace buffer which monitors and captures the response of certain selected signals during run-time. Use of on-chip trace buffers for debug introduces area overhead along with increased power consumption. Thereby, a constraint is imposed on the number of signals selected to be traced. The number of signals to be traced is limited by the width of the trace buffer. The number of samples of each signal traced is limited by the depth of the trace buffer. Hence, it is important to select a set of critical signals to be traced such that number of instances of other signals restored is maximized. In this work, we review some trace signal selection algorithms proposed in the literature and propose several new heuristics. Given constraints on the width and depth, these algorithms attempt to select the best set of signals to maximize the state restoration ratio. We evaluate and the quality and performance of these signal selection algorithms using two different techniques for state restoration: the forward propagation and backward justification (FB) method and the satisfiability (SAT) based method using the standard benchmarks from the literature.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
75 p.
Electrical Engineering
Post-Silicon Validation; Trace signal Selection; Restoration Ratio; Forward-Backward Inference; combined FB-SAT Restoration techniques

Recommended Citations

Citations

  • Tummala, S. (2019). Heuristics for Signal Selection in Post-Silicon Validation [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573573253403988

    APA Style (7th edition)

  • Tummala, Suprajaa. Heuristics for Signal Selection in Post-Silicon Validation. 2019. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573573253403988.

    MLA Style (8th edition)

  • Tummala, Suprajaa. "Heuristics for Signal Selection in Post-Silicon Validation." Master's thesis, University of Cincinnati, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573573253403988

    Chicago Manual of Style (17th edition)

ucin1573573253403988
540
© 2019, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.