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On Reverse Engineering of Encrypted High Level Synthesis Designs

Joshi, Manasi
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049

Abstract Details

2018, MS, University of Cincinnati, Engineering and Applied Science: Electrical Engineering.
Various technical and business challenges make it difficult for every IC company to own and maintain its own foundry. This makes the role of third party foundries very important. Since, the fabrication process involves significant third party handling, the IC design is exposed to various risks and vulnerabilities. The designers send GDSII layout to different foundries for fabrication. In this process there is a huge possibility of presence of malicious foundries, which account for overproduction, counterfeit, theft or inserting trojans. Over the time, significant amount of research has been done to overcome these issues in hardware security. With increased popularity of High-level synthesis, a lot of research is being done for hardware security in high level synthesis. Furthermore, this research can be divided into three main streams, namely, designing an attack methodology, developing attack prevention methods and detecting an inserted trojan. Under 'designing an attack methodology', one state-of-the-art attack claims to decrypt the finite state machine of a design developed through High-level synthesis flow by using Boolean Satisfiability (SAT). This attack formulates a SAT problem by using high level synthesis design constraints, and recovers the correct finite state machine. Few countermeasures have been developed for this threat model which try to harden the FSM of the design in different ways. One of the countermeasures uses decoys to harden the design's finite state machine. The aim of our thesis is to develop a method to decrypt designs with decoy based countermeasure. For our experimentation we used yet another state-of-the-art SAT attack. This SAT attack was originally designed to unlock an encrypted logic design. We used few different approaches to recover the control flow graph of the decoy-encrypted designs. We tried to increase efficiency of SAT attack on our designs by introducing random input patterns and dividing the design into multiple blocks using scan chain configurations.
Ranganadha Vemuri, Ph.D. (Committee Chair)
Wen-Ben Jone, Ph.D. (Committee Member)
Carla Purdy, Ph.D. (Committee Member)
91 p.
Electrical Engineering
Hardware Security; High level synthesis; SAT; Recover flow graph; encrypted high level synthesis

Recommended Citations

Citations

  • Joshi, M. (2018). On Reverse Engineering of Encrypted High Level Synthesis Designs [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049

    APA Style (7th edition)

  • Joshi, Manasi. On Reverse Engineering of Encrypted High Level Synthesis Designs. 2018. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049.

    MLA Style (8th edition)

  • Joshi, Manasi. "On Reverse Engineering of Encrypted High Level Synthesis Designs." Master's thesis, University of Cincinnati, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049

    Chicago Manual of Style (17th edition)

ucin1535466997060049
228
© 2018, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.