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CONFIGURATION BIT STREAM GENERATION FOR THE MT-FPGA & ARCHITECTURAL ENHANCEMENTS FOR ARITHMETIC IMPLEMENTATIONS

SAPRE, VISHAL
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1114616351

Abstract Details

2005, MS, University of Cincinnati, Engineering : Computer Engineering.
Field Programmable Gate Array technology has grown to a stage where entire digital systems with their I/O interfaces can be implemented in single FPGAs. Even so, FPGAs are primarily digital devices with little inbuilt facilities for direct interaction with the analog world. The Multi-Technology FPGA goes beyond this limitation by integrating multi-technology and analog blocks with the regular FPGA fabric. To implement circuits on the MT-FPGA, an automatic configuration bit stream generation system is needed. Designing and implementing such a system has been the point of investigation for this thesis. The major goal in this exercise is to make the system as generic and architecture independent as possible, so as to retarget it to different architectures. The system takes as its input, the output files from FPGA synthesis tools and an architecture specification of the fabric. An XML based architecture specification format and an object-oriented software tool code named “XBits” has been developed. The first part of the thesis explains the specifics of the format and the internals of XBits. Results on academic benchmarks implemented using XBits are also given. As a second part of the thesis, the present MT-FPGA architecture is analyzed for its suitability for large arithmetic circuit implementations. Since the MT-FPGA presents a parallel platform for mapping circuits; signal processing applications that benefit greatly from multiple implementations of functions acting in parallel on long input data streams are of special interest to the MT-FPGA. A new architecture is proposed as a result of this study, which enhances the logic utilization of the FPGA fabric and the speed of arithmetic operations on the MT-FPGA. Associated analysis and comparison of this new architecture with the original architecture is also presented.
Dr. Karen Tomko (Advisor)
125 p.
MT-FPGA; FPGA; Bit Stream; XML

Recommended Citations

Citations

  • SAPRE, V. (2005). CONFIGURATION BIT STREAM GENERATION FOR THE MT-FPGA & ARCHITECTURAL ENHANCEMENTS FOR ARITHMETIC IMPLEMENTATIONS [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1114616351

    APA Style (7th edition)

  • SAPRE, VISHAL. CONFIGURATION BIT STREAM GENERATION FOR THE MT-FPGA & ARCHITECTURAL ENHANCEMENTS FOR ARITHMETIC IMPLEMENTATIONS. 2005. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1114616351.

    MLA Style (8th edition)

  • SAPRE, VISHAL. "CONFIGURATION BIT STREAM GENERATION FOR THE MT-FPGA & ARCHITECTURAL ENHANCEMENTS FOR ARITHMETIC IMPLEMENTATIONS." Master's thesis, University of Cincinnati, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1114616351

    Chicago Manual of Style (17th edition)

ucin1114616351
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© 2005, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.