Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


Dissertation_Susanna Yu.pdf (8.67 MB)

ETD Abstract Container

Abstract Header

Reliability Studies and Development of Improved Design Methodology for Rugged 4H-SiC Power MOSFETs

Yu, Susanna
http://orcid.org/0000-0001-8506-6401
http://rave.ohiolink.edu/etdc/view?acc_num=osu166103441203669

Abstract Details

2022, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
Silicon carbide (SiC) power devices have been emerging as next-generation semiconductors for power electronics with their superior material properties compared to silicon counterparts as well as other wide band gap devices. Among the power devices, metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most desirable semiconductor devices in power switching applications due to their ease of gate drive. As demands for power MOSFETs increase in the industries such as automotive, aerospace, and defense where stringent reliability standards are required, reliability concerns in SiC devices become more pronounced. Reliability concerns in SiC MOSFETs can be divided into two groups: defect-related issues in Metal-Oxide-Semiconductor structure and design trade-off-related issues. Although it is beneficial for SiC to have SiO2 as a native oxide in terms of using advanced silicon process technology, thermally grown SiO2 on SiC contains a large number of interface defects that are introduced by residual carbon. Interface defects and near interface oxide traps are the main cause of low effective inversion layer mobility of SiC MOSFETs and unstable threshold voltage at high temperatures. Moreover, defects in the bulk oxide are also responsible for mobility degradation by Coulomb scattering as well as bias-stress-dependent threshold voltage instability. Commercially available 1.2 kV SiC MOSFETs are evaluated to study the interface traps and near interface oxide traps. It is especially important to examine the trap-induced threshold voltage instability in commercial devices to determine their robustness for automotive applications. Design trade-offs that give rise to the other reliability concerns are also related to the low inversion layer mobility. Short channel length and thin gate oxide adopted to counteract the high on-resistance from the low inversion layer mobility result in low short-circuit time and low screening efficiency of the extrinsic defects in the gate oxide, respectively. In order to understand such design parameter-dependent device characteristics, 2-dimensional process simulations are performed. Design optimization for both active area and termination area preceded the fabrication of 1.2 kV SiC MOSFETs from a commercial foundry. Six different MOSFET designs with different JFET widths and cell pitches are proposed. Fabricated SiC MOSFETs are electrically characterized, and the results are discussed. One of the designs with the narrowest JFET width showed five times higher on-resistance than other designs indicating JFET pinch-off due to either lateral implantation straggle or alignment offset during the fabrication. Forward blocking voltages of all fabricated devices ranged from 600 to 700 V which are half of the desired value, therefore termination design is revisited. Physical analysis is carried out to examine the high on-resistance and low breakdown voltage. Doping profiles are confirmed by Secondary Ion Mass Spectrometry (SIMS) analysis and compared with simulated results. Cross-sectional Scanning Electron Microscopy (SEM) analysis on the active area verified that JFET widths in fabricated devices are narrower than the desired width defined by the mask layout. SEM images on the termination area showed JTE and P+ guard rings are not formed as designed due to alignment offset and implant straggle. Based on the observations, both active and termination structures are modified and re-simulated. Updated simulation results are in good agreement with measurement data. The major conclusion from these studies is that JFET width should be minimized while increasing the n-type doping in the JFET region. It leads to lower CGD which is beneficial for faster switching speed and lower switching losses. Furthermore, it reduces the electric field in the gate oxide during the blocking state which is critical to improve the ruggedness of the SiC MOSFETs for High-Temperature-Reverse-Bias test (HTRB). It also reduces the cell pitch which helps reduce the specific on-resistance. In order to realize this, precise process control should be established.
Agarwal Anant (Advisor)
Julia Zhang (Committee Chair)
Paul Berger (Committee Chair)
Marvin White (Committee Chair)
159 p.
Electrical Engineering
Silicon Carbide; Reliability; Power MOSFETs; 4H-SiC MOSFETs; Interface state density; Near interface traps

Recommended Citations

Citations

  • Yu, S. (2022). Reliability Studies and Development of Improved Design Methodology for Rugged 4H-SiC Power MOSFETs [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu166103441203669

    APA Style (7th edition)

  • Yu, Susanna. Reliability Studies and Development of Improved Design Methodology for Rugged 4H-SiC Power MOSFETs. 2022. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu166103441203669.

    MLA Style (8th edition)

  • Yu, Susanna. "Reliability Studies and Development of Improved Design Methodology for Rugged 4H-SiC Power MOSFETs." Doctoral dissertation, Ohio State University, 2022. http://rave.ohiolink.edu/etdc/view?acc_num=osu166103441203669

    Chicago Manual of Style (17th edition)

osu166103441203669
961
© 2022, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.
Release 3.2.12