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Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation

Tiagaraj, Sathya Narasimman
http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041

Abstract Details

2016, Master of Science, Ohio State University, Electrical and Computer Engineering.
A phase-locked loop (PLL) frequency synthesizer suitable for multi-band transceivers is proposed in this thesis. The multi band frequency synthesizer uses a Voltage Controlled LC Oscillator that is controlled digitally by a Time to Digital Converter, and an analog loop that determines the fine control voltage. The Frequency Synthesizer is a wide band PLL with a reference of 30 MHz and covers a frequency range of 1667 to 2175 MHz with a low average conversion gain of < 45 MHz/V. A key design feature of this wide band PLL frequency synthesizer is that the VCO tuning switches are controlled digitally and the analog charge pump has a calibration circuit to lock itself in the same time as Digital Tuning. It is characterized by behavioral modeling and is implemented on a 90nm CMOS technology with a 1.2 V supply. The system level design tool CppSim was also explored to conclude the ability to transfer the cadence design points to CppSim and vice versa. Various simulations were done to check the performance of the PLL and the results from system level tool CppSim was verified against transistor level implementation. The simulated phase noise is less than -115 dBc/ Hz at 400 KHz offset and the far out of band phase noise is < -155 dBc / Hz at 20 MHz with 5-bit control. Comparison of this multi-band frequency synthesizer with classical AFC control implemented using counters shows a faster lock-in time relative to 25%, an average of 6.5 dB phase noise difference at 400 KHz and 4 dB improvement at far-out phase noise.
Steven Bibyk (Advisor)
Wladimiro Villarroel (Committee Member)
167 p.
Electrical Engineering; Engineering
Frequency Synthesizer, PCS , AWS, CppSim, Phase Locked Loop, Ultra low phase noise, wide band, Digital PLL, Cadence, 90nm, CMOS, VCO, Fractional Spur, Integer N

Recommended Citations

Citations

  • Tiagaraj, S. N. (2016). Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation [Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041

    APA Style (7th edition)

  • Tiagaraj, Sathya Narasimman. Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation. 2016. Ohio State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.

    MLA Style (8th edition)

  • Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." Master's thesis, Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041

    Chicago Manual of Style (17th edition)

osu1461262041
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© 2016, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.
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