In the past several years, technology scaling has reached an impasse, where performance has become limited not by transistor switching delays but by hard limits on power consumption brought on by limits on power delivery, cooling and battery capacities. Although transistors have continued to scale down in size, power density has increased substantially. In the future, it may become impractical to power an entire chip at nominal voltage. The main tool designers have to avoid this power wall is to lower supply voltage, but this combines with the increasing effects of process variation to make semiconductors slower and less reliable. We propose several solutions to these problems.
For logic faults, we provide a tunable reliability target, where the tradeoff between reliability and energy efficiency can be adjusted dynamically for the system, application, and environment. For faults in memories, we develop a new, low-latency forward error correction technique that is a practical solution to the high bit cell failure rate of caches at low voltage. As voltage is lowered, performance is reduced both by generally increasing transistor delay and also by amplifying the effects of process variation; we mitigate the effects of variation through the use of dual voltage supplies and clock dividers. For efficiency, we propose two dual-voltage and dual-frequency techniques for increasing performance of unbalanced workloads. For reliability, we propose an intelligent processor wake-up schedule to eliminate voltage emergencies that can arise from sudden increases in current demand, particularly those associated with common synchronization primitives.