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Thermal Analysis of High-Performance FPGA-Based Multi-Channel Time-To-Digital Converters Based on Tapped Delay Lines Architecture

Alshehry, Awwad Hamdan
http://orcid.org/0009-0001-0867-7791
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1714160438192978

Abstract Details

2024, Doctor of Philosophy (Ph.D.), University of Dayton, Engineering.
We describe a study on the effect of temperature variations on multi-channel Time to Digital Converters (TDC). The objective is to study the impact of ambient thermal variations on the performance of Field Programmable Gate Array (FPGA)-based Tapped Delay Line (TDL) TDC systems, while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study we choose two devices, Xilinx Artix-7 and Microsemi ProASIC3L. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from -75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved Root Mean Square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. We worked to determine the temperature sensitivity for both FPGA devices by observing a significantly low temperature coefficient using Artix-7, while temperature insensitive and stable performance are achieved using the ProASIC3L device. Total on-chip 3 power of 0.968 W was achieved using Artix-7 while less than 1.988 mW of power consumption was achieved using ProASIC3L device. The results and analysis presented in this study convince that the proposed design using the new generations of the FPGAs would help in the design and optimization of FPGA-based TDCs for many applications.
Vamsy Chodavarapu (Advisor)
104 p.
Electrical Engineering; Engineering; Industrial Engineering
field programmable gate arrays; FPGA; RMS resolution; tapped delay line; temperature variations; time to digital converter

Recommended Citations

Citations

  • Alshehry, A. H. (2024). Thermal Analysis of High-Performance FPGA-Based Multi-Channel Time-To-Digital Converters Based on Tapped Delay Lines Architecture [Doctoral dissertation, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1714160438192978

    APA Style (7th edition)

  • Alshehry, Awwad. Thermal Analysis of High-Performance FPGA-Based Multi-Channel Time-To-Digital Converters Based on Tapped Delay Lines Architecture. 2024. University of Dayton, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=dayton1714160438192978.

    MLA Style (8th edition)

  • Alshehry, Awwad. "Thermal Analysis of High-Performance FPGA-Based Multi-Channel Time-To-Digital Converters Based on Tapped Delay Lines Architecture." Doctoral dissertation, University of Dayton, 2024. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1714160438192978

    Chicago Manual of Style (17th edition)

dayton1714160438192978
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© 2024, all rights reserved.
This open access ETD is published by University of Dayton and OhioLINK.