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Design of a Low Power Fractional-N PLL Frequency Synthesizer in 65nm CMOS

Chaille, Jack Ryan
http://orcid.org/0000-0001-6283-6143
http://rave.ohiolink.edu/etdc/view?acc_num=case1649261472101964

Abstract Details

2022, Master of Sciences, Case Western Reserve University, EECS - Electrical Engineering.
Frequency synthesizers play a crucial role in modern wireless communications as the local oscillator in a transceiver’s upconverter and downconverter. One type of frequency synthesizer utilizes a phase-locked loop (PLL) to generate a frequency that is a multiple of a fixed reference. Integer-N PLLs are typically insufficient in modern wireless standards due to tight channel spacing putting a restrictive limit on reference frequency and bandwidth. Fractional-N PLLs, however, can precisely generate an output frequency that is a fractional multiple of the reference by toggling between division ratios. This thesis covers the design and simulation of a 1.2GHz low-power fractional-N PLL-based frequency synthesizer in 65nm CMOS. System-level and circuit-level design choices and simulations are shown, including a true single phase clock phase frequency detector, a charge pump, a 3rd order loop filter, a voltage-controlled oscillator, a toggleable frequency divider, and a 16-bit 2nd order delta sigma modulator.
Hossein Lavasani (Committee Chair)
Christian Zorman (Committee Member)
Pedram Mohseni (Committee Member)
82 p.
Electrical Engineering
PLL; frequency synthesizer; fractional-N; low power; low-power; delta sigma; phase locked loop; phase-locked loop; DSM; delta-sigma

Recommended Citations

Citations

  • Chaille, J. R. (2022). Design of a Low Power Fractional-N PLL Frequency Synthesizer in 65nm CMOS [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1649261472101964

    APA Style (7th edition)

  • Chaille, Jack. Design of a Low Power Fractional-N PLL Frequency Synthesizer in 65nm CMOS. 2022. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1649261472101964.

    MLA Style (8th edition)

  • Chaille, Jack. "Design of a Low Power Fractional-N PLL Frequency Synthesizer in 65nm CMOS." Master's thesis, Case Western Reserve University, 2022. http://rave.ohiolink.edu/etdc/view?acc_num=case1649261472101964

    Chicago Manual of Style (17th edition)

case1649261472101964
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© 2022, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.